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US 12,119,822 B2Granted
Signal generation circuit having minimum delay, semiconductor apparatus using the same, and signal generation method
AssigneeSK hynix Inc.
InventorsYoung Ouk Kim, Gyu Tae Park
Life of this patent
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Abstract
A signal generation circuit includes a first delay circuit, a second delay circuit, and a duty control circuit. The first delay circuit delays a first input signal to generate a first output signal. The second delay circuit delays a second input signal to generate a second output signal. The duty control circuit compares phases of the first and second output signals and changes the value of the second delay control signal, and then decreases the times, by which the first and second input signals are delayed, by the same value.
Claims17
A semiconductor apparatus comprising:
- a clock divider configured to generate a first divided clock signal and a second divided clock signal by dividing an input clock signal;
- a first duty correction circuit configured to generate a first reference clock signal and a second reference clock signal by delaying the first and second divided clock signals, compare the phases of the first and second reference clock signals to adjust a delay time of the second divided clock signal by a first time, and then decrease a delay time of the first divided clock signal and the delay time of the second divided clock signal by a second time;
- and
- a delay locked loop circuit configured to compare the phases of the first reference clock signal and a feedback clock signal and generate at least one output clock signal by delaying the first and second reference clock signals, and generate the feedback clock signal by delaying the at least one output clock signal.
1 more element
A semiconductor apparatus comprising:
- a clock divider configured to generate a first divided clock signal and a second divided clock signal by dividing an input clock signal;
- a first duty correction circuit configured to generate a first reference clock signal by delaying the first divided clock signal based on a first delay control signal, configured to generate a second reference clock signal by delaying the second divided clock signals based on a second delay control signal, compare the phases of the first and second reference clock signals to change a value of the second delay control signal, and then decrease values of the first and second delay control signals by the same value;
- and
- a delay locked loop circuit configured to compare the phases of the first reference clock signal and a feedback clock signal and generate at least one output clock signal by delaying the first and second reference clock signals, and generate the feedback clock signal by delaying the at least one output clock signal.
1 more element
Dependencies are inferred from the claim text.