Gate driver circuits with independently tunable performance characteristics

A solid-state circuit breaker, comprising:

• a first output terminal;
• a second output terminal;
• at least one gate driver configured to generate a turn-on signal VGON and a turn-off signal VGOFF;
• a pair of anti-series solid-state switches selectively coupling the first output terminal with the second output terminal;
• and
• a gate driver circuit coupled to the at least one gate driver and a first solid-state switch of the pair of anti-series solid-state switches, the gate driver circuit comprising:
• a turn-on circuit path coupled between a gate of the first solid-state switch and VGON, wherein the turn-on circuit path defines a turn-on time for the first solid-state switch;
• a turn-off circuit path coupled between the gate of the first solid-state switch and VGOFF, wherein the turn-off circuit path defines a turn-off time for the first solid-state switch;
• and
• a fast discharge circuit path selectively coupled in parallel with the turn-off circuit path during a portion of a gate-to-source voltage (VGS) transition for the first solid-state switch, wherein the turn-off circuit path in parallel with the fast discharge circuit path defines a turn-off delay for the first solid-state switch,
• wherein each of the turn-on time, the turn-off time, and the turn-off delay are independently configurable.

An apparatus comprising:

• a gate driver configured to generate a turn-off signal VGOFF;
• a solid-state switch including a gate, a drain, and a source;
• a turn-off circuit path coupled between the gate of the solid-state switch and VGOFF;
• and
• a fast discharge circuit path comprising one of:
• a first circuit comprising a first resistor having a first terminal coupled to VGOFF and a second terminal, a n-channel Field-Effect Transistor (FET) having a drain coupled to the gate of the solid-state switch, a source coupled to the second terminal of the first resistor, and a gate, a first Zener diode having a cathode coupled to the drain of the n-channel FET and an anode coupled to the gate of the n-channel FET, and a second resistor having a third terminal coupled to the gate of the n-channel FET and a fourth terminal coupled to the source of the n-channel FET;
• and
• a second circuit comprising a third resistor having a fifth terminal coupled to VGOFF and a sixth terminal, a p-channel FET having a source coupled to the gate of the solid-state switch, a drain coupled to the sixth terminal of the third resistor, and a gate, a fourth resistor having a seventh terminal coupled to the source of the p-channel FET and a eighth terminal coupled to the gate of the p-channel FET, a fifth resistor having a ninth terminal coupled to the gate of the p-channel FET and a tenth terminal, and a second Zener diode having a cathode coupled to the tenth terminal of the fifth resistor and an anode coupled to a source of the solid-state switch.