Single carrier pulse width modulator for 5-level converter with capacitor voltage self-balancing, equal loss distribution, and improved output voltage spectrum

A multi-level power rectifier having a DC output and at least one AC phase input comprising:

• two DC capacitors connected in series with said DC output, said DC capacitors, in operation, being charged to one half of a voltage of said DC output;
• for each one of said at least one AC phase input:
• a ground or neutral terminal connected to a midpoint between said two DC capacitors connected in series;
• a pair of power switches S3 connected in series across a first one of said two DC capacitors;
• a pair of power switches S4 connected in series across a second one of said two DC capacitors;
• a flying capacitor, in operation, being charged to one quarter of a voltage of said DC output;
• a pair of power switches S2, a first one of said power switches S2 connected between a midpoint between said power switches S3 and a first terminal of said flying capacitor and a second one of said power switches S2 connected between a midpoint between said power switches S4 and a second terminal of said flying capacitor;
• a pair of power switches S1, a first one of said power switches S1 connected between the first terminal of said flying capacitor and one of said at least one AC phase input, and a second one of said power switches S1 connected between the second terminal of said flying capacitor and said one of said at least one AC phase input;
• and
• a current controller receiving phase and current measurements from said at least one AC phase input, a desired DC voltage signal and producing at least one reference waveform signal for each of said at least one AC phase input;
• a modulator having an input for receiving said at least one reference waveform signal for each of said at least one AC phase input and having gate signal outputs connected to each of said pairs of power switches S1 through S4, wherein said modulator, in operation, produces said gate signal outputs without sensor feedback, cause the flying capacitor to be equally charged and discharged in each pulse-width modulation period for voltage balancing of the flying capacitor, and causes the switching time of said pairs of power switches S3 and S4 to be equal to balance the voltages on said two DC capacitors while canceling odd multiples of a switching harmonic cluster frequency and doubling the switching harmonic cluster frequency.

A motor controller comprising:

• a rectifier for converting AC power to DC power;
• a multi-level power inverter connected to said rectifier, said multi-level power inverter having a DC input and at least one AC phase output comprising for each one of said at least one AC phase output:
• two DC capacitors connected in series with said DC input, said DC capacitors, in operation, being charged to one half of a voltage of said DC input;
• a ground or neutral terminal connected to a midpoint between said two DC capacitors connected in series;
• a pair of power switches S3 connected in series across a first one of said two DC capacitors;
• a pair of power switches S4 connected in series across a second one of said two DC capacitors;
• a flying capacitor, in operation, being charged to one quarter of a voltage of said DC input;
• a pair of power switches S2, a first one of said power switches S2 connected between a midpoint between said power switches S3 and a first terminal of said flying capacitor and a second one of said power switches S2 connected between a midpoint between said power switches S4 and a second terminal of said flying capacitor;
• a pair of power switches S1, a first one of said power switches S1 connected between the first terminal of said flying capacitor and one of said at least one AC phase output, and a second one of said power switches S1 connected between the second terminal of said flying capacitor and said one of said at least one AC phase output;
• and
• a modulator having an input for receiving a reference waveform signal and gate signal outputs connected to each of said pairs of power switches S1 through S4, wherein said modulator, in operation, produces said gate signal outputs without sensor feedback, cause the flying capacitor to be equally charged and discharged in each pulse-width modulation period for voltage balancing of the flying capacitor, and causes the switching time of said pairs of power switches S3 and S4 to be equal to balance the voltages on said two DC capacitors while canceling odd multiples of a switching harmonic cluster frequency and doubling the switching harmonic cluster frequency;
• and
• a controller connected to a motor sensor and to said input of said modulator input for providing said a reference waveform signal.