US 12,119,640 B2Granted

ESD protection circuit

AssigneeHuawei Technologies Co., Ltd.

InventorsWei Gao, Hongquan Sun, Wangsheng Xie

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Abstract

An electrostatic discharge (ESD) protection circuit is provided to minimize ESD damage to an internal circuit in a CDM model. The ESD protection circuit includes two stages of discharging circuits that are coupled to an IO pin and the internal circuit, a first power clamp circuit, and a second power clamp circuit. The first power clamp circuit is electrically connected to a power rail and a ground rail to discharge a part of a current to the ground, and the second power clamp circuit is electrically connected to a second-stage discharging circuit and the ground rail, so that the other part of the current is discharged to the ground through the second power clamp circuit.

Claims14

Dependent claims

An electrostatic discharge (ESD) protection circuit, wherein the ESD protection circuit comprises:

a first-stage discharging circuit that is electrically connected to an IO pin, a power rail, and a ground rail;
a first power clamp circuit that is electrically connected to the power rail and the ground rail;
a second-stage discharging circuit that is electrically connected to a protected circuit, and the ground rail;
and
a second power clamp circuit that is electrically connected to the second-stage discharging circuit and the ground rail,
wherein
the ESD protection circuit further comprises a bias resistor,
a current input terminal of the second power clamp circuit is electrically connected to the second-stage discharging circuit and a first terminal of the bias resistor,
a pull-down terminal of the second power clamp circuit is electrically connected to the ground rail, and
a second terminal of the bias resistor is electrically connected to the power rail.

7 more elements

An apparatus, comprising a chip and an electrostatic discharge (ESD) protection circuit, wherein

the chip comprises an IO pin and a protected circuit, and
the ESD protection circuit comprises:
a first-stage discharging circuit that is electrically connected to the IO pin, a power rail, and a ground rail;
a first power clamp circuit that is electrically connected to the power rail and the ground rail;
a second-stage discharging circuit that is electrically connected to the protected circuit, and the ground rail;
and
a second power clamp circuit that is electrically connected to the second-stage discharging circuit and the ground rail,
the ESD protection circuit further comprises a bias resistor,
a current input terminal of the second power clamp circuit is electrically connected to the second-stage discharging circuit and a first terminal of the bias resistor,
a pull-down terminal of the second power clamp circuit is electrically connected to the ground rail, and
a second terminal of the bias resistor is electrically connected to the power rail.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/831,763Filed 3 Jun 2022 · continuation
Priority: 6 Dec 2019
Published: US 2022/0294213 A115 Sep 2022
Granted: 15 Oct 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H02H 9/046
Adapted to a particular application and not provided for elsewhere: responsive to excess voltage appearing at terminals of integrated circuits
H10D 89/611
For devices having insulated gate electrodes, e.g. for IGFETs or IGBTs: using diodes as protective elements
H10D 89/811
For devices having insulated gate electrodes, e.g. for IGFETs or IGBTs: using FETs as protective elements
H02H
Emergency protective circuit arrangements

Family

PCT/CN2019/123806Parent of this continuation · filed 6 Dec 2019
US 2022/0294213 A1Pre-grant publication · published 15 Sep 2022
US 12,119,640 B2This patent

From the US filing history. Foreign family members aren’t listed.

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