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US 12,119,411 B2Granted
NAND flash memory with vertical cell stack structure and method for manufacturing same
AssigneeMosaid Technologies Incorporated
InventorHyoung Seub Rhie
Life of this patent
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Abstract
Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.
Claims17
A NAND Flash memory device with a vertical cell stack structure comprising:
- a cell substrate layer;
- a first n-type conductive region within the cell substrate layer;
- a stack of layers disposed over the cell substrate layer, and comprising:
- a bottom insulating layer,
- a bottom gate layer over the bottom insulating layer,
- intermediate gate layers over the bottom gate layer, the intermediate gate layers insulated from each other by intermediate insulating layers, wherein the intermediate gate layers are horizontally separated by a dielectric-filled vertical slit to form a first stack of word lines extending in a first horizontal direction and a second stack of word lines extending in the first horizontal direction, the first stack of word lines and the second stack of word lines being arranged side-by-side in a second horizontal direction perpendicular to the first horizontal direction,
- a top gate layer over the intermediate gate layers, and
- a top insulating layer over the top gate layer, the top insulating layer comprising a different material than the intermediate insulating layers, or having a different thickness than the intermediate insulating layers, or both;
- and
- a first plurality of cell pillars, the first plurality of cell pillars including a first and a second cell pillar arranged in the second horizontal direction, each of the first plurality of cell pillars extending through the stack of layers and partially into the cell substrate layer past a top surface of the cell substrate layer, each of the first plurality of cell pillars comprising:
- a pillar body comprising a poly silicon film, and extending into the cell substrate layer to a level below the top surface of the cell substrate layer such that sidewalls of the pillar body are in contact with the first n-type conductive region;
- an interior pillar region disposed within the pillar body and surrounded by the poly silicon film, the interior pillar region extending to a level below the top surface of the cell substrate layer, wherein the interior pillar region comprises a dielectric filler material;
- and
- gate dielectric material surrounding the pillar body, the gate dielectric material comprising a tunnel dielectric layer in physical contact with the pillar body, a charge trap layer surrounding the tunnel dielectric layer, and a coupling layer surrounding the charge trap layer, the gate dielectric material terminating at locations above the top surface of the cell substrate layer;
- wherein the first cell pillar extends through the first stack of word lines and the second cell pillar extends through the second stack of word lines;
- and wherein the first n-type conductive region continuously extends in the second horizontal direction underneath the vertical slit to contact the first cell pillar and the second cell pillar.
13 more elements
A NAND Flash memory device with a vertical cell stack structure comprising:
- a cell substrate layer;
- a first n-type conductive region within the cell substrate layer;
- a first and a second cell pillar, each of the first and the second cell pillars comprising:
- a pillar body comprising a poly silicon film, and extending into the cell substrate layer to a level below the top surface of the cell substrate layer such that sidewalls of the pillar body are in contact with the first n-type conductive region;
- an interior pillar region disposed within the pillar body and surrounded by the poly silicon film, the interior pillar region extending to a level below the top surface of the cell substrate layer, wherein the interior pillar region is non-conductive;
- wherein the first cell pillar extends through a first stack of word lines and the second cell pillar extends through a second stack of word lines, the first stack of word lines and the second stack of word lines being arranged side-by-side with a dielectric-filled vertical slit intervening between the first stack of word lines and the second stack of word lines.
3 more elements
Dependencies are inferred from the claim text.