Multi-layer crystalline back gated thin film transistor

An integrated circuit comprising:

• a gate structure including a gate dielectric above a gate electrode;
• a stack of layers on the gate dielectric and including (i) a first layer comprising a crystalline material, and (ii) a second layer below the first layer and comprising an amorphous material;
• a source at least partially on a first portion of an upper surface of the stack of layer;
• and
• a drain at least partially on a second portion of the upper surface of the stack of layer.

An integrated circuit comprising:

• a gate structure including a gate dielectric above a gate electrode, the gate dielectric including a high-K dielectric material;
• a stack of layers above and on the high-K dielectric material of the gate dielectric, the stack of layers including first, second, and third layers, the first and third layers comprising crystalline material, and the second layer comprising an amorphous material, wherein the second layer is between the first and third layers and in direct contact with the first and third layers;
• a source at least partially on a first portion of an upper surface of the stack of layers;
• a drain at least partially on a second portion of the upper surface of the stack of layers;
• a first layer of insulator material adjacent a sidewall of the stack of layers;
• and
• a second layer of insulator material laterally between the source and the drain.