US 12,119,390 B2 · Gate spacer structures and methods for forming the same

Abstract

The present disclosure relates to a semiconductor device including a substrate having a top surface and a gate stack. The gate stack includes a gate dielectric layer on the substrate and a gate electrode on the gate dielectric layer. The semiconductor device also includes a multi-spacer structure. The multi-spacer includes a first spacer formed on a sidewall of the gate stack, a second spacer, and a third spacer. The second spacer includes a first portion formed on a sidewall of the first spacer and a second portion formed on the top surface of the substrate. The second portion of the second spacer has a thickness in a first direction that gradually decreases. The third spacer is formed on the second portion of the second spacer and on the top surface of the substrate. The semiconductor device further includes a source/drain region formed in the substrate, and a portion of the third spacer abuts the source/drain region and the second portion of the second spacer.

Claims20

Dependent claims

A semiconductor device, comprising:

a substrate;
a gate stack, comprising:
a gate dielectric layer disposed on the substrate;
and
a gate electrode disposed on the gate dielectric layer;
a multi-spacer structure, comprising:
a first spacer disposed on a sidewall of the gate stack;
a second spacer comprising a first spacer portion disposed on a sidewall of the first spacer and a second spacer portion disposed on the substrate, wherein the second spacer portion has a thickness that decreases along a top surface of the substrate;
and
a third spacer disposed on the second spacer portion and in contact with the substrate;
and
a source/drain region formed in the substrate, wherein a portion of the third spacer abuts the source/drain region and the second spacer portion.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/858,968Filed 6 Jul 2022 · division

Priority

31 Jan 2019

Published

US 2022/0336629 A120 Oct 2022

Granted

15 Oct 2024

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10D 64/021
Manufacture or treatment: using multiple gate spacer layers, e.g. bilayered sidewall spacers
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
H10D 62/021
Manufacture or treatment: forming source or drain recesses by etching e.g. recessing by etching and then refilling

Family

Application62/799,453Us provisional application · filed 31 Jan 2019

Application16/690,005Parent of this division · filed 20 Nov 2019

US 2022/0336629 A1Pre-grant publication · published 20 Oct 2022

US 11,437,493 B2Parent of this division

US 11,393,914 B2Related patent

US 2020/0251571 A1Published application

US 12,119,390 B2This patent

From the US filing history. Foreign family members aren’t listed.

Gate spacer structures and methods for forming the same

Life of this patent

Gate spacer structures and methods for forming the same

Life of this patent

Abstract

Claims20