Semiconductor device with reduced trap defect and method of forming the same

A method of manufacturing a semiconductor device, comprising:

• providing a substrate comprising fins;
• forming a dummy gate electrode over the fins;
• forming a gate spacer to surround the dummy gate electrode;
• depositing a first dielectric layer to cover the gate spacer, the dummy gate electrode and the substrate;
• depositing a second dielectric layer over the first dielectric layer;
• forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer subsequent to depositing the second dielectric layer;
• etching recesses in the substrate through the first dielectric layer and the LDD regions;
• forming source/drain regions in the recesses;
• removing the second dielectric layer to expose the gate spacer subsequent to forming the source/drain regions;
• forming a replacement gate through removing the dummy gate electrode;
• forming contact plugs to electrically couple to the replacement gate and the source/drain regions;
• and
• introducing a hydrogen gas to perform a first annealing operation on the semiconductor device.

A method of manufacturing a semiconductor device, comprising:

• providing a semiconductor fin comprising a channel region;
• forming a patterned dummy gate over the semiconductor fin;
• forming a first dielectric layer over the patterned dummy gate and the channel region;
• etching a portion of the first dielectric layer to form a gate spacer;
• forming lightly-doped source/drain (LDD) regions in the semiconductor fin on two sides of the patterned dummy gate;
• depositing a second dielectric layer over the patterned dummy gate, the gate spacer and the LDD regions;
• forming source/drain regions extending through second dielectric layer and the respective LDD regions;
• forming a replacement gate in place with the patterned dummy gate;
• forming an inter-layer dielectric layer over the source/drain regions and the replacement gate;
• and
• subsequent to the forming of the inter-layer dielectric layer, performing an annealing operation on the semiconductor device in a hydrogen ambient.