Gate all around transistors with different threshold voltages

A method, comprising:

• forming a first active region over a p-type well of a substrate and a second active region over an n-type well over of the substrate, wherein each of the first active region and the second active region comprises a plurality of silicon layers interleaved by a plurality of silicon germanium layer;
• forming a dummy gate stack over channel regions of the first active region and the second active region;
• performing a dummy gate cut process to form a first dielectric feature and a second dielectric feature through the dummy gate stack to define a dummy gate segment sandwiched between the first dielectric feature and the second dielectric feature;
• and
• removing the dummy gate stack without substantially etching the first dielectric feature and the second dielectric feature;
• selectively removing the plurality of silicon germanium layers in the first active region or the second active region to release the plurality of silicon layers as a first plurality of nanostructures over the p-type well and a second plurality of nanostructures over the n-type well;
• thinning the first plurality of nanostructures and the second plurality of nanostructures;
• and
• after the thinning, forming a first gate structure to wrap around each of the first plurality of nanostructures and a second gate structure to wrap around each of the second plurality of nanostructures.

A method, comprising:

• providing a workpiece comprising:
• a first stack of semiconductor layers and a second stack of semiconductor layers over a first area of a substrate, each of the first stack and the second stack comprising a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers, and
• a third stack of semiconductor layers and a fourth stack of semiconductor layers over a second area of the substrate, each of the third stack and the fourth stack comprising the plurality of first semiconductor layers interleaved by the plurality of second semiconductor layers;
• forming a first dummy gate stack over the first stack and the second stack;
• forming a second dummy gate stack over the third stack and the fourth stack;
• performing a gate cut process to form a first dielectric feature and a second dielectric feature such that the first stack and the second stack are disposed between the first dielectric feature and the second dielectric feature, and a third dielectric feature and a fourth dielectric feature such that the third stack and the fourth stack are disposed between the third dielectric feature and the fourth dielectric feature;
• selectively removing the first dummy gate stack and the second dummy gate stack without substantially etching the first dielectric feature, the second dielectric feature, the third dielectric feature, and the fourth dielectric feature;
• selectively removing the plurality of second semiconductor layers to release the plurality of first semiconductor layers in the first stack, the second stack, the third stack, and the fourth stack as first channel members, second channel members, third channel members, and fourth channel members, respectively;
• selectively thinning the first channel members and the second channel members while the third channel members and the fourth channel members are covered by a dielectric filler and a hard mask layer;
• after the selectively thinning, removing the dielectric filler and the hard mask layer;
• after the removing of the dielectric filler and the hard mask layer, forming a first gate dielectric layer to wrap around the first channel members and the second channel members and a second gate dielectric layer to wrap around the third channel members and the fourth channel members;
• and
• forming a first gate structure to wrap around each of the first channel members, a second gate structure to wrap around each of the second channel members, a third gate structure to wrap around each of the third channel members, and fourth gate structure to wrap around the fourth channel members.