Power semiconductor device having vertically parallel p-n layers formed in an active region under transistor cells and under a non-depletable extension zone formed in the edge region

A semiconductor device, comprising:

• a semiconductor body comprising:
• a drain layer extending to a rear surface of the semiconductor body;
• a drift zone disposed over the drain layer and having a lower dopant concentration than the drain layer;
• an active area comprising one or more transistor cells, each of the transistor cells comprising source zones disposed over the drift zone and extending to a main surface of the semiconductor body that is opposite from the rear surface, and a gate configured to control a conductive channel between the source zones and the drain layer;
• wherein the semiconductor device exhibits a first output charge gradient when a voltage between the drain layer and the source zones increases from a depletion voltage of the semiconductor device to a maximum drain/source voltage of the semiconductor device,
• wherein the semiconductor device exhibits a second output charge gradient when a voltage between the drain layer and the source zones of the semiconductor device decreases from the maximum drain/source voltage to the depletion voltage of the semiconductor device, and
• wherein the semiconductor device is configured such that the first output charge gradient deviates by less than 5% from the second output charge gradient.