US 12,119,374 B2Granted

Semiconductor device

AssigneeSamsung Electronics Co., Ltd.

InventorsGihee Cho, Sangyeol Kang, Jungoo Kang, Taekyun Kim, Jiwoon Park, Sanghyuck Ahn, Jin-Su Lee, Hyun-Suk Lee, Hongsik Chae

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Abstract

A semiconductor device and a method of manufacturing the same, the device including a plurality of lower electrodes on a semiconductor substrate; a support pattern connecting the lower electrodes at sides of the lower electrodes; and a dielectric layer covering the lower electrodes and the support pattern, wherein each of the plurality of lower electrodes includes a pillar portion extending in a vertical direction perpendicular to a top surface of the semiconductor substrate; and a protrusion protruding from a sidewall of the pillar portion so as to be in contact with the support pattern, the pillar portion includes a conductive material, the protrusion includes a same conductive material as the pillar portion and is further doped with impurities.

Claims20

Dependent claims

A semiconductor device, comprising:

a substrate;
a first insulating layer on the substrate;
a contact structure in the first insulating layer;
a second insulating layer on the first insulating layer;
a lower electrode on the second insulating layer, passing through the second insulating layer, and electrically connected to the contact structure, the lower electrode including a first connection portion and a second connection portion that is on the first connection portion and that is spaced apart from the first connection portion in a vertical direction that is perpendicular to a top surface of the substrate;
a first support pattern on the second insulating layer and connected to the first connection portion of the lower electrode;
a second support pattern on the first support pattern and connected to the second connection portion of the lower electrode;
a dielectric layer on the lower electrode;
and
an upper electrode on the dielectric layer,
wherein:
a top surface of the first connection portion of the lower electrode and a bottom surface of the first connection portion of the lower electrode contact the dielectric layer, and
a top surface of the second connection portion of the lower electrode and a bottom surface of the second connection portion of the lower electrode contact the dielectric layer.

10 more elements

A semiconductor device, comprising:

substrate;
an insulating layer on the substrate;
a lower electrode on the insulating layer, the lower electrode including a first connection portion, a second connection portion that is on the first connection portion and that is spaced apart from the first connection portion, and a side surface between the first connection portion and the second connection portion;
a first support pattern connected to the first connection portion of the lower electrode;
a second support pattern connected to the second connection portion of the lower electrode;
a dielectric layer on the lower electrode;
and
an upper electrode on the dielectric layer,
wherein:
a thickness of the first support pattern in a vertical direction that is perpendicular to a top surface of the substrate is less than a thickness of the second support pattern in the vertical direction,
a thickness of the first connection portion of the lower electrode in the vertical direction is less than a thickness of the second connection portion of the lower electrode in the vertical direction, and
the dielectric layer contacts a top surface of the first connection portion of the lower electrode, a bottom surface of the second connection portion of the lower electrode, and the side surface of the lower electrode.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/857,383Filed 5 Jul 2022 · continuation
Priority: KR 10-2020-009479929 Jul 2020
Published: US 2022/0037461 A120 Oct 2022
Granted: 15 Oct 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10D 1/043
Of capacitors having no potential barriers: using patterning processes to form electrode extensions, e.g. etching
H10B 12/033
Making the capacitor or connections thereto: the capacitor extending over the transistor
H10B 12/0335
The capacitor extending over the transistor: making a connection between the transistor and the capacitor, e.g. plug
H10B 12/053
Making the transistor: the transistor being at least partially in a trench in the substrate

Family

Application17/189,700Parent of this continuation · filed 2 Mar 2021
US 2022/0336578 A1Pre-grant publication · published 20 Oct 2022
US 11,411,075 B2Parent of this continuation
US 2022/0037461 A1Published application
US 12,119,374 B2This patent

From the US filing history. Foreign family members aren’t listed.

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