Capacitance matched metal wirings in dual conversion gain pixels

A system, comprising:

• a light source;
• and
• an imaging device including:
• a pixel including:
• a photoelectric conversion region;
• a first transfer transistor coupled to the photoelectric conversion region to transfer charge generated by the photoelectric conversion region;
• a first floating diffusion coupled to the first transfer transistor;
• a second floating diffusion;
• a second transfer transistor coupled between the first floating diffusion and the second floating diffusion to control access to the second floating diffusion;
• a third transfer transistor coupled to the photoelectric conversion region to transfer charge generated by the photoelectric conversion region;
• a third floating diffusion coupled to the second transfer transistor;
• a fourth floating diffusion;
• and
• a fourth transfer transistor coupled between the third floating diffusion and the fourth floating diffusion to control access to the fourth floating diffusion;
• and
• a first wiring layer including:
• a first wiring connected to the second floating diffusion;
• a second wiring connected to the fourth floating diffusion;
• and
• a third wiring connected to ground and capacitively coupled with the first wiring and the second wiring.

An imaging device, comprising:

• a pixel including:
• a photoelectric conversion region;
• a first transfer transistor coupled to the photoelectric conversion region to transfer charge generated by the photoelectric conversion region;
• a first floating diffusion coupled to the first transfer transistor;
• a second floating diffusion;
• a second transfer transistor coupled between the first floating diffusion and the second floating diffusion to control access to the second floating diffusion;
• a third transfer transistor coupled to the photoelectric conversion region to transfer charge generated by the photoelectric conversion region;
• a third floating diffusion coupled to the second transfer transistor;
• a fourth floating diffusion;
• and
• a fourth transfer transistor coupled between the third floating diffusion and the fourth floating diffusion to control access to the fourth floating diffusion;
• and
• a first wiring layer including:
• a first wiring connected to the second floating diffusion;
• a second wiring connected to the fourth floating diffusion;
• and
• a third wiring connected to ground and capacitively coupled with the first wiring and the second wiring, wherein the first wiring, the second wiring, and the third wiring form a symmetrical pattern.