US 12,119,350 B2Granted

Semiconductor structure and method for forming semiconductor structure

AssigneeChangxin Memory Technologies, Inc.

InventorsKui Zhang, Xin Li, Zhan Ying

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Abstract

A semiconductor structure includes a base and conductive channel structure which includes first and second conductive channel layers and conductive buffer layer. The first conductive channel layer includes a first conductive channel, first and second doped regions on both sides of the first conductive channel; the second conductive channel layer includes a second conductive channel and third and fourth doped regions on both sides of the second conductive channel; the conductive buffer layer reduces electrical interference between the first and third doped regions. The semiconductor structure further includes a first wire layer disposed on the base extending in a direction and in contact with the second doped region; a second wire layer extending in another direction and in contact with the first and third doped regions; and a gate structure disposed around the first and second conductive channels.

Claims19

Dependent claims

A semiconductor structure comprising:

a base and a conductive channel structure on the base, the conductive channel structure comprising a first conductive channel layer, a conductive buffer layer, and a second conductive channel layer stacked in sequence,
wherein the first conductive channel layer comprises a first conductive channel, a first doped region and a second doped region on both sides of the first conductive channel, wherein the first doped region is close to the second conductive channel layer;
the second conductive channel layer comprises a second conductive channel, and a third doped region and a fourth doped region on both sides of the second conductive channel, wherein the third doped region is close to the first conductive channel layer;
and
the conductive buffer layer is configured to reduce electrical interference between the first doped region and the third doped region;
a first wire layer, disposed on the base, extending in a first direction, and in contact with the second doped region in the first direction;
a second wire layer, extending in a second direction, and in contact with the first doped region and the third doped region in the second direction;
a gate structure, disposed around the first conductive channel and the second conductive channel;
and
a protective layer, nested on top of all of separate conductive channel structures, in contact with the fourth doped region, and having a via penetrating the protective layer in a direction perpendicular to a surface of the base, the via being filled with the gate structure.

7 more elements

A method for forming a semiconductor structure, comprising:

providing a base comprising a structure region and a wiring region, wherein the base comprises a substrate, a first wire layer extending in a first direction and an isolation layer;
forming a first sacrificial layer on the base in the structure region, and forming a peripheral insulating structure on the base in the wiring region;
patterning the first sacrificial layer to form a first channel penetrating through the first sacrificial layer;
forming a second wire layer, which fills the first channel and is partially disposed on the first sacrificial layer, extends into the peripheral insulating structure of the wiring region, and extends in a second direction;
sequentially forming a second sacrificial layer and a protective layer on the base in the structure region;
patterning the second sacrificial layer to form a second channel penetrating through the second sacrificial layer, and projections of the first channel and the second channel on the base overlap with each other;
forming a second conductive channel layer filling the second channel;
patterning a part of the protective layer to expose the second sacrificial layer, and removing the second sacrificial layer and the first sacrificial layer;
and
forming a gate structure which fills a gap between a plane where the first wire layer is disposed and a plane where the second wire layer.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/449,493Filed 30 Sep 2021 · continuation
Priority: CN 202110336399.029 Mar 2021
Published: US 2022/0310596 A129 Sep 2022
Granted: 15 Oct 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification23 codes

H10D 30/025
Of FETs having insulated gates [IGFET]: of vertical IGFETs
H10D 84/856
Complementary IGFETs, e.g. CMOS: the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
H10D 30/019
Manufacture or treatment: of FETs having stacked nanowire, nanosheet or nanoribbon channels
H10D 30/031
Of FETs having insulated gates [IGFET]: of thin-film transistors [TFT]

Family

PCT/CN2021/112012Parent of this continuation · filed 11 Aug 2021
US 2022/0310596 A1Pre-grant publication · published 29 Sep 2022
US 12,119,350 B2This patent

From the US filing history. Foreign family members aren’t listed.

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