Semiconductor integrated circuit device
AssigneeSocionext Inc.
InventorYoko Shiraki
Life of this patent
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Abstract
A layout structure of a standard cell using a complementary FET (CFET) is provided. The standard cell includes a first three-dimensional transistor and a second three-dimensional transistor formed above the first transistor in the depth direction, between buried first and second power supply lines. A first contact connects a local interconnect connected to the first transistor and the first power supply line. A second contact connects a local interconnect connected to the second transistor and the second power supply line. The second contact is longer in the depth direction and greater in size in planar view than the first contact.
Claims11
A semiconductor integrated circuit device including a standard cell, the standard cell comprising:
- a first line extending in a first direction in a first wiring layer;
- a second line extending in the first direction in the first wiring layer;
- a first transistor that is a three-dimensional transistor of a first conductivity type, formed above the first wiring layer in a depth direction;
- a second transistor that is a three-dimensional transistor of a second conductivity type, formed above the first transistor in the depth direction;
- a first contact connected to one of a source and a drain of the first transistor and the first line;
- a second contact connected to one of a source and a drain of the second transistor and the second line,
- wherein
- the second contact is longer in the depth direction than the first contact and greater in size in planar view than the first contact.
A semiconductor integrated circuit device including a standard cell, the standard cell comprising:
- a first line extending in a first direction in a first wiring layer;
- a first transistor that is a three-dimensional transistor of a first conductivity type, formed above the first wiring layer in a depth direction;
- a second transistor that is a three-dimensional transistor of a second conductivity type, formed above the first transistor in the depth direction;
- a first local interconnect connected to one of a source and a drain of the first transistor;
- a second local interconnect connected to one of a source and a drain of the second transistor;
- a first contact formed at a position where the first local interconnect and the second local interconnect overlap each other as viewed in plan, for connecting the first local interconnect and the second local interconnect;
- and
- a second contact connected to another of a source and a drain of the second transistor and the first line,
- wherein
- the second contact is greater in size in planar view than the first contact.
Dependencies are inferred from the claim text.