Fusion memory device and method of fabricating the same

A method of fabricating a fusion memory device, the method comprising:

• forming a first memory cell circuit including a plurality of first memory cells on an active surface of a first substrate;
• forming a non-memory circuit including a plurality of peripheral transistors on an active surface of a second substrate, and a plurality of conductive lines electrically connected to the peripheral transistors;
• and
• combining the first memory cell circuit with the non-memory circuit,
• wherein forming the first memory cell circuit includes:
• performing a diffusion process on the active surface of the first substrate at a first temperature;
• vertically stacking a plurality of gate electrodes on the active surface of the first substrate;
• forming a plurality of vertical channels vertically penetrating the plurality of gate electrodes, each of the vertical channels being surrounded by a memory layer;
• forming a plurality of common source plugs electrically connected to the active surface of the first substrate;
• and
• forming a plurality of electrical lines electrically connected to the gate electrodes, the vertical channels, and the common source plugs,
• wherein combining the first memory cell circuit with the non-memory circuit includes:
• aligning a first outer terminal of the first memory cell circuit, which is electrically connected to at least one of the electrical lines, with a second outer terminal of the non-memory circuit, which is electrically connected to at least one of the conductive lines;
• and
• bonding the first outer terminal to the second outer terminal.

A method of fabricating a fusion memory device, the method comprising:

• forming a first memory cell circuit including a plurality of first memory cells on an active surface of a first semiconductor substrate;
• forming a non-memory circuit including a plurality of conductive lines on an active surface of a second semiconductor substrate;
• combining the first memory cell circuit with the non-memory circuit;
• and
• forming a second memory cell circuit including a plurality of second memory cells on an inactive surface of the second semiconductor substrate,
• wherein forming the first memory cell circuit includes:
• performing a diffusion process on the active surface of the first semiconductor substrate at a first temperature;
• and
• forming a plurality of common source plugs electrically connected to the active surface of the first semiconductor substrate, and
• wherein forming the second memory cell circuit excludes a diffusion process.