Semiconductor package

A semiconductor package, comprising:

• an interposer substrate having a first surface and a second surface that are opposite to each other, the interposer substrate including a wiring layer adjacent to the first surface;
• a first semiconductor chip and a second semiconductor chip that are horizontally spaced apart from each other on the first surface of the interposer substrate;
• a passivation layer on the first surface of the interposer substrate, the passivation layer covering the first semiconductor chip and the second semiconductor chip;
• and
• a plurality of redistribution patterns in the passivation layer, the plurality of redistribution patterns connecting the first semiconductor chip to the second semiconductor chip,
• wherein the first semiconductor chip has a third surface and a fourth surface that are opposite to each other, the first semiconductor chip including:
• a plurality of first chip pads adjacent to the third surface;
• a first semiconductor substrate on the plurality of first chip pads;
• a plurality of first chip through electrodes penetrating the first semiconductor substrate and spaced apart from each other in the first semiconductor substrate;
• and
• a first circuit layer on the first semiconductor substrate,
• wherein the second semiconductor chip has a fifth surface and a sixth surface that are opposite to each other, the second semiconductor chip including:
• a plurality of second chip pads adjacent to the fifth surfaces;
• a second semiconductor substrate on the plurality of second chip pads;
• a plurality of second chip through electrodes penetrating the second semiconductor substrate and spaced apart from each other in the second semiconductor substrate;
• and
• a second circuit layer on the second semiconductor substrate,
• wherein each of the plurality of first chip pads and the plurality of second chip pads are directly connected to a corresponding one of a plurality of wiring patterns in the wiring layer of the interposer substrate, and
• wherein the plurality of redistribution patterns are connected to the fourth surface of the first semiconductor chip and to the sixth surface of the second semiconductor chip.

A semiconductor package, comprising:

• an interposer substrate having a first surface and a second surface that are opposite to each other, the interposer substrate including a wiring layer adjacent to the first surface;
• a first semiconductor chip and a second semiconductor chip that are horizontally spaced apart from each other on the first surface of the interposer substrate;
• a passivation layer on the first surface of the interposer substrate, the passivation layer covering the first semiconductor chip and the second semiconductor chip;
• a third semiconductor chip on the passivation layer;
• a plurality of conductive pillars below the third semiconductor chip;
• and
• a plurality of redistribution patterns in the passivation layer, the plurality of redistribution patterns connecting the first semiconductor chip to the second semiconductor chip,
• wherein the first semiconductor chip has a third surface and a fourth surface that are opposite to each other, the first semiconductor chip including a plurality of first chip pads adjacent to the third surface,
• wherein the second semiconductor chip has a fifth surface and a sixth surface that are opposite to each other, the second semiconductor chip including a plurality of second chip pads adjacent to the fifth surface,
• wherein each of the plurality of first chip pads and the plurality of second chip pads are directly bonded to a corresponding one of a plurality of wiring patterns in the wiring layer,
• wherein the plurality of redistribution patterns are connected to the fourth surface of the first semiconductor chip and to the sixth surface of the second semiconductor chip,
• wherein the plurality of conductive pillars penetrate through the passivation layer and connect with the wiring layer of the interposer substrate, and
• wherein the plurality of conductive pillars are connected to corresponding ones of the plurality of wiring patterns in the wiring layer.