Methods of fabricating the same die stack structure and semiconductor structure

A method for fabricating a die stack structure, comprising:

• bonding a semiconductor die to a first surface of a semiconductor wafer;
• forming first grooves on the first surface of the semiconductor wafer, wherein a depth of the first grooves is smaller than a thickness of the semiconductor wafer;
• forming an insulating encapsulation to encapsulate the semiconductor die and fill the first grooves;
• forming a redistribution circuit structure on a second surface of the semiconductor wafer, wherein the first surface is opposite to the second surface;
• forming second grooves, wherein the second grooves extend through the redistribution circuit structure;
• and
• performing a wafer sawing process to saw the semiconductor wafer and insulating encapsulation.

A method, comprising:

• bonding top tier semiconductor dies to a semiconductor wafer comprising bottom tier semiconductor dies, each of the bottom tier semiconductor dies comprising a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate;
• forming first grooves on the semiconductor wafer, the first grooves extending through the interconnect structures of the bottom tier semiconductor dies into the semiconductor substrates of the bottom tier semiconductor dies, and the semiconductor substrates of the bottom tier semiconductor dies being revealed by the first grooves;
• forming an insulating encapsulation over the semiconductor wafer to laterally encapsulate the top tier semiconductor dies and fill the first grooves to form a reconstructed wafer;
• forming a redistribution circuit structure on the reconstructed wafer to be electrically connected with the top tier semiconductor dies and the bottom tier semiconductor dies;
• and
• performing a wafer sawing process to saw the reconstructed wafer along scribe lines of the semiconductor wafer to separate the bottom tier semiconductor dies, wherein a maximum lateral dimension of the first grooves is wider than a maximum cutting width of the wafer sawing process, each of the semiconductor substrates of the bottom tier semiconductor dies comprises a first portion and a second portion disposed on the first portion, each of the interconnect structures of the bottom tier semiconductor dies is disposed on a top surface of the corresponding second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion, the insulating encapsulation is located on the first portion and laterally encapsulating the second portion, and the lateral dimension of the first portion is greater than a lateral dimension of the redistribution circuit structure.