US 12,119,325 B2Granted

Semiconductor device assemblies with molded support substrates

AssigneeMicron Technology, Inc.

InventorsMitsuhisa Watanabe, Fumitomo Watanabe, Masanori Yoshida

Life of this patent

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Abstract

Semiconductor device assemblies with molded support substrates and associated methods are disclosed herein. In one embodiment, a semiconductor device assembly includes a support substrate, a first semiconductor die embedded within the support substrate, a second semiconductor die coupled to the support substrate, and a third semiconductor die coupled to the support substrate. The assembly can also include a redistribution network formed on a first and/or second side of the support substrate, and a plurality of conductive contacts electrically coupled to at least one of the first, second or third semiconductor dies.

Claims18

Dependent claims

A semiconductor device assembly, comprising:

a support substrate having a bottom surface;
a first semiconductor die at least partially embedded within the support substrate and configured to route signals across a thickness of the support substrate, wherein the first semiconductor die includes:
a die top surface with a top contact thereon, the top contact for coupling to circuits external to the first semiconductor die, and
a die bottom surface embedded within the support substrate and located over a bottom surface of the support substrate;
at least one interconnect extending partially through the support substrate and between the die bottom surface and the bottom surface of the support substrate;
a second semiconductor die attached to the support substrate;
a die stack attached to the support substrate;
and
a plurality of conductive contacts attached to the support substrate opposite the second semiconductor die, wherein a portion of the conductive contacts are electrically coupled to the second semiconductor die and/or one or more dies in the die stack through the first semiconductor die.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/224,234Filed 7 Apr 2021 · continuation
Priority: 6 Apr 2017
Published: US 2021/0225805 A122 Jul 2021
Granted: 15 Oct 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification26 codes

H10W 90/00
Package configurations
H10W 70/09
By depositing layers on the chip or wafer, e.g. "chip-first" RDLs: extending onto an encapsulation that laterally surrounds the chip or wafer,…
H10W 70/60
Package substrates; Interposers; Redistribution layers [RDL]: insulating or insulated package substrates; Interposers; Redistribution layers
H10W 70/614
For connecting multiple chips together: the multiple chips being integrally enclosed

Family

Application15/481,331Parent of this continuation · filed 6 Apr 2017
Application16/243,995Parent of this continuation · filed 9 Jan 2019
US 10,217,719 B2Parent of this continuation · filed 26 Feb 2019
US 2021/0225805 A1Pre-grant publication · published 22 Jul 2021
US 10,998,290 B2Parent of this continuation
US 2018/0294249 A1Published application
US 2019/0148338 A1Published application
US 12,119,325 B2This patent

From the US filing history. Foreign family members aren’t listed.

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