US 12,119,324 B2 · Package structure

Abstract

A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.

Claims20

Dependent claims

A package structure, comprising:

an interposer, comprising:
a semiconductor substrate comprising a first bulk portion and a second bulk portion disposed on the first bulk portion;
and
an interconnect structure disposed on the second bulk portion, wherein a first sub-portion of the second bulk portion comprises first sidewalls, a second sub-portion of the second bulk portion comprises second sidewalls, and the first sidewalls and second sidewalls are different in slope, wherein the first sidewalls substantially linearly extend from a top surface of the semiconductor substrate to the second sidewalls, and the second sidewalls are substantially perpendicular to the top surface of the semiconductor substrate;
at least one semiconductor die disposed over and electrically connected to the interconnect structure;
and
an insulating encapsulation disposed on the interposer and laterally encapsulating the least one semiconductor die.

4 more elements

A package structure, comprising:

an interposer comprising a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, wherein the semiconductor substrate comprises a first bulk portion and a second bulk portion, the second bulk portion is between the first bulk portion and the interconnect structure, first tapered sidewalls of the interconnect structure and second tapered sidewalls of a first sub-portion of the second bulk portion are substantially equal in slope, the second tapered sidewalls of the first sub-portion of the second bulk portion and sidewalls of a second sub-portion of the second bulk portion are different in slope, wherein the second tapered sidewalls of the first sub-portion of the second bulk portion substantially linearly extends from a top surface of the semiconductor substrate to the sidewalls of the second sub-portion of the second bulk portion, and the sidewalls of the second sub-portion of the second bulk portion are substantially perpendicular to the top surface of the semiconductor substrate;
at least one semiconductor die disposed over and electrically connected to the interconnect structure;
and
an insulating encapsulation disposed on the interposer and encapsulating the least one semiconductor die.

1 more element

Dependencies are inferred from the claim text.

Package structure

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Package structure

Life of this patent

Abstract

Claims20