Packaging structure of semiconductor chip and formation method thereof

A packaging structure, comprising:

• a base plate, wiring structures in the base plate, input terminals on a front surface of the base plate, and output terminals on a back surface of the base plate, wherein the input terminals and the output terminals are connected to corresponding wiring structures respectively;
• semiconductor chips mounted on the front surface of the base plate inversely, wherein each semiconductor chip includes a functional surface, and a non-functional surface opposite to the functional surface, soldering pads on the functional surface, and a metal bump on each soldering pad, wherein each metal bump is connected to a corresponding input terminal on the front surface of the base plate;
• a bottom filling layer between a functional surface of each semiconductor chip and the front surface of the base plate;
• a first shielding layer surrounding the non-functional surface and sidewalls of each semiconductor chip and a corresponding bottom filling layer;
• a second shielding layer on each first shielding layer;
• a bottom shielding layer and an isolation layer, interlaced along a lateral direction of the base plate between the functional surface of each semiconductor chip and the bottom filling layer, wherein
• the bottom shielding layer includes edges being in contact with a sidewall of the first shielding layer, and
• each soldering pad penetrates through the interlaced isolation layer;
• and
• external contact structures connected to the output terminals and on the back surface of the base plate.

A discrete packaging structure formed by cutting a package structure, comprising:

• a base plate, wiring structures in the base plate, input terminals on a front surface of the base plate, and output terminals on a back surface of the base plate, wherein the input terminals and the output terminals are connected to corresponding wiring structures respectively;
• a semiconductor chip mounted on the front surface of the base plate inversely, wherein the semiconductor chip includes a functional surface, a non-functional surface opposite to the functional surface, soldering pads on the functional surface, and a metal bump on each soldering pad, wherein each metal bump is connected to a corresponding input terminal on the front surface of the base plate;
• a bottom filling layer between the functional surface of the semiconductor chip and the front surface of the base plate;
• a first shielding layer surrounding the non-functional surface and sidewalls of the semiconductor chip and a corresponding bottom filling layer;
• a second shielding layer on the first shielding layer;
• a bottom shielding layer and an isolation layer, interlaced along a lateral direction of the base plate between the functional surface of each semiconductor chip and the bottom filling layer, wherein
• the bottom shielding layer includes edges being in contact with a sidewall of the first shielding layer, and
• each soldering pad penetrates through the interlaced isolation layer;
• and
• external contact structures connected to the output terminals and on the back surface of the base plate.