US 12,119,301 B2Granted

Semiconductor device

AssigneeSocionext Inc.

InventorsWenzhen Wang, Atsushi Okamoto, Hirotaka Takeno

Life of this patent

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Abstract

A semiconductor device includes a chip that includes a substrate and a first interconnection layer on a surface of the substrate; and a second interconnection layer on another surface opposite to the surface of the substrate. The second interconnection layer includes a first power line having a first power potential, a second power line having a second power potential, and a switch between the first power line and the second power line. The chip includes a first grounding line, a third power line having the second power potential, a first region having the first grounding line and the third power line, a second grounding line, a fourth power line having the first power potential, and a second region having the second grounding line and the fourth power line. In plan view, the switch is between the first region and the second region.

Claims15

Dependent claims

A semiconductor device, comprising:

a first chip including a substrate and a first interconnection layer formed on a first surface of the substrate;
and
a second interconnection layer formed on a second surface opposite to the first surface of the substrate,
wherein
the second interconnection layer includes
a first power line to which a first power potential is applied,
a second power line to which a second power potential is applied, and
a switch connected between the first power line and the second power line,
the first chip includes
a first grounding line,
a third power line to which the second power potential is applied,
a first region in which the first grounding line and the third power line are disposed,
a second grounding line,
a fourth power line to which the first power potential is applied, and
a second region in which the second grounding line and the fourth power line are disposed, and
in plan view, the switch is disposed between the first region and the second region.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/716,299Filed 8 Apr 2022 · continuation
Priority: 11 Oct 2019
Published: US 2022/0230954 A121 Jul 2022
Granted: 15 Oct 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10W 20/427
Characterised by their conductive parts: power or ground buses
H10W 20/43
Characterised by their conductive parts: layouts of interconnections
H10D 89/10
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated device layouts
H10W 20/20
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]

Family

PCT/JP2019/040258Parent of this continuation · filed 11 Oct 2019
US 2022/0230954 A1Pre-grant publication · published 21 Jul 2022
US 12,119,301 B2This patent

From the US filing history. Foreign family members aren’t listed.

Timeline

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