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US 12,119,300 B2Granted
Transistor circuits with shielded reference transistors
AssigneeNXP USA, Inc.
InventorsHumayun Kabir, Ibrahim Khalil, Daniel Joseph Lamey, Yu-Ting David Wu
Life of this patent
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Abstract
A device having a reference transistor fabricated within the same semiconductor substrate as a primary transistor (e.g., configured for use in a radiofrequency amplifier or other active circuit) has a shared metallization area coupled to a current terminal of both transistors configured to shield a control terminal of the reference transistor from coupling of alternating current interference from alternating currents within the primary transistor.
Claims18
A semiconductor device, comprising:
- a primary transistor formed within a semiconductor substrate, the primary transistor having a first current terminal, a second current terminal, and a control terminal;
- a reference transistor adjacent to the primary transistor formed within the semiconductor substrate, the reference transistor having a first current terminal, a second current terminal, and a control terminal;
- and
- a bias controller configured to operate the primary transistor at a desired operating point by:
- applying predetermined bias voltages to the current terminals and the control terminal of the reference transistor;
- measuring a reference electrical current level flowing between the first current terminal and the second current terminal of the reference transistor;
- and
- applying bias voltages configured to operate the primary transistor at the desired operating point that are derived from the reference current level to the primary transistor;
- wherein the device further comprises:
- a first gate metallization area of the semiconductor substrate that is electrically coupled to the control terminal of the primary transistor;
- a second gate metallization area of the semiconductor substrate that is electrically coupled to the control terminal of the reference transistor;
- and
- a shared metallization area of the semiconductor substrate that is coupled to both the first current terminal of the primary transistor and to the first current terminal of the reference transistor;
- wherein the shared metallization area includes a metallized extension that is disposed between the first gate metallization area and the second gate metallization area and the metallized extension is configured to shield the control terminal of the reference transistor from alternating-current signals applied to the current terminal of the primary transistor;
- and
- wherein the shared metallization area is configured such that the first current terminal of the reference transistor is electrically coupled to the first current terminal of the primary transistor through the shared metallization area.
13 more elements
A semiconductor device, comprising:
- a primary transistor formed within a semiconductor substrate, the primary transistor having a first current terminal, a second current terminal, and a control terminal;
- a reference transistor adjacent to the primary transistor formed within the semiconductor substrate, the reference transistor having a first current terminal, a second current terminal, and a control terminal;
- a first gate metallization area of the semiconductor substrate that is electrically coupled to the control terminal of the primary transistor;
- a second gate metallization area of the semiconductor substrate that is electrically coupled to the control terminal of the reference transistor;
- and
- a shared metallization area of the semiconductor substrate that is coupled to both the first current terminal of the primary transistor and to the first current terminal of the reference transistor;
- wherein the shared metallization area includes a first metallized extension that is disposed between the first gate metallization area and the second gate metallization area and the first metallized extension is configured to shield the control terminal of the reference transistor from alternating-current signals applied to the current terminal of the primary transistor;
- and
- wherein the shared metallization area is configured such that the first current terminal of the reference transistor is electrically coupled to the first current terminal of the primary transistor through the shared metallization area.
6 more elements
A method of forming a semiconductor device, comprising:
- forming a primary transistor within a semiconductor substrate, the primary transistor having a first current terminal, a second current terminal, and a control terminal;
- forming a reference transistor adjacent to the primary transistor within the semiconductor substrate, the reference transistor having a first current terminal, a second current terminal, and a control terminal;
- forming a first gate metallization area of the semiconductor substrate that is electrically coupled to the control terminal of the primary transistor;
- forming a second gate metallization area of the semiconductor substrate that is electrically coupled to the control terminal of the reference transistor;
- and
- forming a shared metallization area of the semiconductor substrate that is coupled to both the first current terminal of the primary transistor and to the first current terminal of the reference transistor;
- wherein forming the shared metallization area includes forming a first metallized extension that is disposed between the first gate metallization area and the second gate metallization area;
- wherein the first metallized extension is configured to shield the control terminal of the reference transistor from alternating-current signals applied to the current terminal of the primary transistor;
- and
- wherein the shared metallization area is configured such that the first current terminal of the reference transistor is electrically coupled to the first current terminal of the primary transistor through the shared metallization area.
7 more elements
Dependencies are inferred from the claim text.