Semiconductor memory device

A semiconductor memory device comprising:

• a substrate expanding in a first direction and a second direction and including a first area and a second area arranged in the first direction, the first direction intersecting the second direction;
• a plurality of conductive layers arranged in a third direction with a distance therebetween, the third direction intersecting the first direction and the second direction, the conductive layers including a first conductive layer and a second conductive layer provided along the third direction with at least one conductive layer of the conductive layers interposed therebetween and each of the conductive layers including a first portion and a second portion arranged with the first portion in the second direction, the first portion extending in the first direction over the second area and the second portion including a terrace portion provided so as not to overlap an upper conductive layer of the conductive layers in the third direction;
• a first insulating layer arranged in a same layer as a first upper conductive layer above the first conductive layer and provided between the first portion of the first conductive layer and the terrace portion of the first conductive layer in the second direction, the first upper conductive layer being included in the conductive layers and adjacent to the first conductive layer in the third direction;
• a second insulating layer arranged in a same layer as a second upper conductive layer above the second conductive layer, provided between the first portion of the second conductive layer and the terrace portion of the second conductive layer in the second direction, and arranged with the first insulating layer in the third direction with a distance therebetween, the second upper conductive layer being included in the conductive layers and adjacent to the second conductive layer in the third direction;
• and
• a first memory pillar passing through the conductive layers in the third direction in the first area, a portion of the first memory pillar intersecting the first conductive layer functioning as a first memory cell transistor.