Array of vertical transistors having channel regions connected by an elongated conductor line

An array of vertical transistors, comprising:

• spaced first pillars individually comprising a channel region of individual vertical transistors and an upper source/drain region directly above the channel region;
• a conductor line horizontally-elongated in a column direction directly electrically coupling together individual of the channel regions of the first pillars of a plurality of the vertical transistors, the conductor line comprising spaced conductive second pillars projecting upwardly from a continuous line of conductor material of the conductor line;
• a lower source/drain region below the individual channel regions of the first pillars;
• and
• a conductive gate line operatively aside the individual channel regions of the first pillars and that interconnects multiple of the vertical transistors in a row direction.