High voltage devices

A semiconductor device, comprising:

• a substrate;
• a plurality of core devices over the substrate, each of the plurality of core devices including a first active region extending along a first direction;
• a first plurality of input/output (I/O) transistors over the substrate, each of the first plurality of I/O transistors including a second active region extending along the first direction;
• a second plurality of I/O transistors over the substrate, each of the second plurality of I/O transistors including a third active region extending along the first direction;
• a first gate structure wrapping around the first active region and extending along a second direction perpendicular to the first direction;
• and
• a second gate structure wrapping around the second active region and extending along the second direction,
• where the first active region includes a first width along the second direction, the second active region includes a second width along the second direction, and the third active region includes a third width along the second direction,
• wherein the first width is equal to the second width,
• wherein the third width is greater than the first width.

A semiconductor structure, comprising:

• a semiconductor substrate including a first device region and a second device region;
• a first plurality of transistors in the first device region, each of the first plurality of transistor including two semiconductor fins extending in parallel along a first direction and spaced apart from one another along a second direction perpendicular to the first direction;
• a second plurality of transistors in the second device region, each of the second plurality of transistors including a semiconductor mesa extending lengthwise along the first direction;
• a first gate structure wrapping around each of the two semiconductor fins and extending lengthwise along the second direction;
• a second gate structure wrapping around the semiconductor mesa and extending lengthwise along the second direction;
• a third plurality of transistors in a third device region disposed between the first device region and the second device region, each of the third plurality of transistors including a wide semiconductor fin extending along the first direction;
• and
• a third gate structure wrapping around the wide semiconductor fin,
• wherein the first gate structure and the second gate structure are aligned and spaced apart from one another along the second direction and have a same dimension along the first direction to give appearance that the first gate structure and the second structure are divided from a single gate structure,
• wherein one of the first plurality of transistors is adjacent one of the second plurality of transistors,
• where each of the two semiconductor fins includes a first width along the second direction and the semiconductor mesa includes a second width along the second direction,
• wherein the second width is greater than the first width,
• wherein the first gate structure is spaced apart from the semiconductor fin by a leftover dummy gate dielectric layer,
• wherein the second gate structure is disposed directly on the semiconductor mesa,
• wherein the two semiconductor fins and the semiconductor mesa rise continuously from the semiconductor substrate,
• wherein the wide semiconductor fin comprises a third width along the second direction,
• wherein the third width is greater than the first width and smaller than the second width.