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US 12,119,080 B1Granted
Extended-burst write training
AssigneeCadence Design Systems, Inc.
InventorsSreeja Menon, Nikhil Raghavendra Rao, Srinivas Shanmukha Gundlapalli
Life of this patent
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Abstract
A control component transmits a timing strobe and associated write data burst to a memory component, extending the write data burst to include a quantity of successive bits in excess of active edges in the timing strobe to ensure that the write data burst is sampled under worst-case timing skew conditions.
Claims20
A memory control integrated circuit (IC) comprising:
- a command interface to transmit a write command to a memory component;
- and
- a data interface to transmit to the memory component in association with the write command:
- a data strobe having a preamble and a first quantity of data-timing transitions that immediately follow the preamble;
- and
- a data burst constituted by a second quantity of data symbols transmitted in respective, successive symbol-transmission intervals, the second quantity exceeding the first quantity.
3 more elements
A method of operation within a memory control component, the method comprising:
- transmitting a write command to a memory component;
- transmitting a data strobe to the memory component in association with the write command, the data strobe having a preamble and a first quantity of data-timing transitions that immediately follow the preamble;
- and
- transmitting a data burst to the memory component in association with the write command, the data burst constituted by a second quantity of data symbols transmitted in respective, successive symbol-transmission intervals, the second quantity exceeding the first quantity.
1 more element
Dependencies are inferred from the claim text.