Circuits and methods of mitigating hold time failure of pipeline for memory device

A device comprising:

• a clock control circuit having a first output to provide a clock signal;
• a first pulse generator including a first input coupled to the first output of the clock control circuit through a first metal rail, the first pulse generator to generate a memory clock signal to control one or more memory cells, based on a first delayed clock signal, the first delayed clock signal delayed with respect to the clock signal by the first metal rail;
• and
• a second pulse generator including:
• a second input coupled to the first output of the clock control circuit through a second metal rail to receive a second delayed clock signal delayed with respect to the clock signal by the second metal rail, and
• a third input coupled to a second output of the first pulse generator to receive the memory clock signal,
• wherein the second pulse generator is to generate a pipeline clock signal based on the second delayed clock signal and the memory clock signal, the pipeline clock signal to control a pipeline to provide data from the one or more memory cells.

A method comprising:

• generating, by a memory controller based on a first delayed clock signal, a memory clock signal to control one or more memory cells, the first delayed clock signal delayed with respect to a clock signal;
• generating, by the memory controller based on a second delayed clock signal and the memory clock signal, a pipeline clock signal to provide data from the one or more memory cells through a pipeline, the second delayed clock signal delayed with respect to the clock signal;
• performing, by the memory controller, an OR operation on the second delayed clock signal and the memory clock signal to generate a control signal, the pipeline clock signal generated based on the control signal;
• enabling, by the memory controller, current through a node according to the control signal, a voltage at the node corresponding to the pipeline clock signal;
• and
• providing, by the memory controller, the data from the one or more memory cells through the pipeline, according to the pipeline clock signal.