Data processing circuit and semiconductor memory divided into segments

A semiconductor memory, comprising the data processing circuit, wherein the data processing circuit comprises a primary transmission path, a plurality of secondary transmission paths and a plurality of storage arrays, wherein the plurality of storage arrays share the primary transmission path,

• each of the plurality of storage arrays comprises at least two sub-arrays, and the secondary transmission path is formed between each sub-array and the primary transmission path, and the sub-array transmits a data signal through the secondary transmission path corresponding to the sub-array and the primary transmission path;
• wherein each of the plurality of storage arrays comprises a first sub-array and a second sub-array, and the primary transmission path passes through an intermediate area between the first sub-array and the second sub-array,
• the primary transmission path comprises a first primary transmission path and a second primary transmission path, the first primary transmission path is close to the first sub-array, and the second primary transmission path is close to the second sub-array, and
• the secondary transmission path comprise a first secondary transmission path and a second secondary transmission path, wherein the secondary transmission path connected with the first primary transmission path is defined as the first secondary transmission path, and the secondary transmission path connected with the second primary transmission path is defined as the second secondary transmission path, the first secondary transmission path includes the path between the first sub-array and the first primary transmission path and the path between the second sub-array and the first primary transmission path, the second secondary transmission path includes the path between the first sub-array and the second primary transmission path and the path between the second sub-array and the second primary transmission path.