Semiconductor integrated circuit

A semiconductor integrated circuit configured to transmit and receive data to and from a plurality of memory cells associated with word lines and bit lines in a semiconductor memory device, the semiconductor integrated circuit comprising:

• a plurality of sense amplifier units, including a first group of sense amplifier units and a second group of sense amplifier units, wherein each of the sense amplifier units is connected to one of the bit lines;
• a first data bus connected to each of the sense amplifier units in the first group;
• a second data bus connected to each of the sense amplifier units in the second group;
• a transfer circuit that is connected between the first data bus and the second data bus and controlled to invert and transfer data in a first direction from the first data bus to the second data bus and to transfer data in a second direction from the second data bus to the first data bus without inversion, the transfer circuit including an inverter circuit that is connected between the first data bus and the second data bus and is controlled to enable transmission of data from the first data bus to the second data bus therethrough during the data transfer in the first direction and to block the transmission of data from the first data bus to the second data bus therethrough during the data transfer in the second direction;
• and
• a data latch that is connected to the second data bus, and to the first data bus through the second data bus and the transfer circuit.