Efficient soft decoding of error correction code via extrinsic bit information

A memory system comprising:

• a non-volatile memory;
• and
• a controller for performing operations of the non-volatile memory, the controller being configured to:
• select a plurality of memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second page including a second plurality of bits;
• modify, based on the first plurality of bits and the second plurality of bits, a first voltage threshold corresponding to a read voltage for the first plurality of bits;
• allocate, to a voltage range bounded by the first voltage threshold, a log-likelihood ratio (LLR);
• and
• decode, based on the LLR corresponding to the voltage range, the first plurality of bits.

A non-transitory computer readable medium including one or more instructions stored thereon and executable by a processor to:

• select, by a processor, a plurality of memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second page including a second plurality of bits;
• modify, by the processor and based on the first plurality of bits and the second plurality of bits, a first voltage threshold corresponding to a read voltage for the first plurality of bits;
• allocate, by the processor to a voltage range bounded by the first voltage threshold, a log-likelihood ratio (LLR);
• and
• decode, by the processor and based on the LLR corresponding to the voltage range, the first plurality of bits.