Back to results
US 12,119,074 B2Granted
Data correction of redundant data storage
AssigneeTexas Instruments Incorporated
InventorTimothy Duryea
Life of this patent
Estimating the term…
Abstract
In one example, an apparatus comprises first, second and third memory devices, an error detection circuit, and an error correction circuit. The error detection circuit is configured to detect a mismatch among data stored at the first, second, and third memory devices, and responsive to detecting the mismatch, provide a correction signal representing a majority state of the data. The error correction circuit is configured to write the majority state of the data into at least one of the first, second, or third memory devices responsive to the correction signal.
Claims20
An apparatus comprising:
- a first memory device having a first data input and a first data output;
- a second memory device having a second data input and a second data output;
- a third memory device having a third data input and a third data output;
- an error detection circuit having a first detection input, a second detection input, a third detection input, and a detection output, the first detection input coupled to the first data output, the second detection input coupled to the second data output, and the third detection input coupled to the third data output, the error detection circuit configured to:
- detect a mismatch among data stored at the first, second, and third memory devices;
- and
- responsive to detecting the mismatch, provide a correction signal at the detection output, the correction signal representing a majority state of the data;
- and
- an error correction circuit having a correction input, a first correction output, a second correction output, and a third correction output, the correction input coupled to the detection output, the first correction output coupled to the first data input, the second correction output coupled to the second data input, the third correction output coupled to the third data input, and the error correction circuit configured to write the majority state of the data into at least one of the first, second, or third memory devices.
6 more elements
An apparatus comprising:
- a first memory device configured to store a first copy of first data;
- a second memory device configured to store a second copy of the first data;
- a third memory device configured to store a third copy of the first data;
- an instruction memory configured to store a set of instructions;
- and
- a processor configured to execute the set of instructions to:
- detect a mismatch between the first, second, and third copies of the first data stored at the respective first, second, and third memory devices;
- generate a correction signal representing an uncorrupted state of the first data;
- determine whether second data is received;
- responsive to determining that the second data is received, store copies of the second data at the first, second, and third memory devices;
- and
- responsive to determining that the second data is not received, provide the correction signal to at least one of the first, second, or third memory devices to write the uncorrupted state of the first data into at least one of the first, second, or third memory devices.
9 more elements
A method comprising:
- detecting a mismatch among copies of first data stored in a set of memory devices;
- generating a correction signal representing an uncorrupted state of the first data;
- determining whether second data is received;
- responsive to determining that the second data is received, writing copies of the second data into the set of memory devices;
- and
- responsive to determining that the second data is not received, providing the correction signal to at least one memory device of the set of memory devices to write the uncorrupted state of the first data into the at least one memory device.
3 more elements
Dependencies are inferred from the claim text.