Anti-fuse memory reading circuit with controllable reading time

An anti-fuse memory reading circuit with controllable reading time comprising an anti-fuse memory cell, wherein the anti-fuse memory reading circuit comprises a reading time control circuit, a programmable reading pulse generation circuit, a reading amplification circuit, and a reading register;

• the reading time control circuit generates a control signal and provides the control signal to the programmable reading pulse generation circuit and the reading amplification circuit, wherein the control signal has K control bits and corresponds to a reading time;
• based on a clock signal, the programmable reading pulse generation circuit generates a reading pulse with a pulse width corresponding to the control signal and outputs the reading pulse to the reading amplification circuit;
• and
• the reading amplification circuit comprises a plurality of pull-up current sources of different sizes, wherein based on the reading pulse and the control signal, the reading amplification circuit selects a pull-up current source corresponding to the reading time, pulls up a voltage on a bit line (BL) of the anti-fuse memory cell, reads data stored in the anti-fuse memory cell starting from a rising edge of the reading pulse, and latches the read data into the reading register at a falling edge of the reading pulse.