Memory device and operation method thereof

A memory device comprising:

• a first voltage generator configured to output a first voltage;
• a second voltage generator configured to output a second voltage;
• a switch circuit configured to selectively connect an output of the first voltage generator with first driving lines and to connect an output of the second voltage generator with second driving lines;
• a memory block connected with a plurality of wordlines;
• and
• an address decoding circuit configured to connect the first driving lines with first unselected wordlines of the plurality of wordlines and to connect the second driving lines with second unselected wordlines of the plurality of wordlines, wherein
• the switch circuit is configured to connect the output of the first voltage generator with the first driving lines and to float the first driving lines when the output of the first voltage generator reaches a first target level, and
• the switch circuit is configured to connect the output of the second voltage generator with the second driving lines and to float the second driving lines when the output of the second voltage generator reaches a second target level, and
• the second target level is different from the first target level.

An operation method of a memory device which includes a memory block connected with a plurality of wordlines, the method comprising:

• applying a first voltage to unselected wordlines of the plurality of wordlines, the first voltage being generated from a first voltage generator;
• floating first unselected wordlines of the unselected wordlines when the first unselected wordlines reach a first target level;
• and
• floating second unselected wordlines of the unselected wordlines when the second unselected wordlines reach a second target level, the second target level being higher than the first target level.