Read algorithms for three-dimensional crosspoint memory architectures

A memory module comprising:

• input/output (I/O) circuitry to couple the memory module with an external controller;
• and
• a plurality of non-volatile memory devices, each memory device comprising:
• a plurality of non-volatile memory cells, each memory cell comprising a phase change material (PM) region and a select device (SD) region in series with the PM region;
• address lines to apply voltages across the memory cells, wherein each memory cell has a corresponding address line pair to apply voltages thereto;
• and
• memory controller circuitry to interface with the address lines of the memory cells, the memory controller circuitry to read a state in a memory cell by:
• ramping a voltage applied to a first address line of the address line pair corresponding to the memory cell until the first address line voltage is stabilized at a predetermined voltage;
• ramping a voltage applied to a second address line of the address line pair corresponding to the memory cell;
• detecting a snap in the memory cell while ramping the voltage applied to the second address line;
• and
• determining a state of the memory cell based on a differential voltage between the first and second address lines when the memory cell snap occurred.

A memory controller comprising:

• circuitry interface with address lines of a memory cell comprising a phase change material (PM) region and a select device (SD) region in series, the circuitry to read a state in a memory cell by:
• ramping a voltage applied to a first address line of an address line pair corresponding to the memory cell until the first address line voltage is stabilized at a predetermined voltage;
• ramping a voltage applied to a second address line of the address line pair corresponding to the memory cell;
• detecting a snap in the memory cell while ramping the voltage applied to the second address line;
• and
• determining a state of the memory cell based on a differential voltage between the first and second address lines when the memory cell snap occurred.

A method of reading a state in a memory cell comprising a phase change material (PM) region and a select device (SD) region in series, the method comprising:

• ramping a voltage applied to a first address line of an address line pair corresponding to the memory cell until the first address line voltage is stabilized at a predetermined voltage;
• ramping a voltage applied to a second address line of the address line pair corresponding to the memory cell;
• detecting a snap in the memory cell while ramping the voltage applied to the second address line;
• and
• determining a state of the memory cell based on a differential voltage between the first and second address lines when the memory cell snap occurred.