Method of programming MLC memory device and related MLC memory device

A multi-level cell (MLC) memory device, comprising:

• a memory array comprising M columns and N rows of memory cells, wherein M and N are integers larger than 1;
• and
• a processing circuit configured to:
• acquire threshold voltage variations of each row of memory cells among the N rows of memory cells according to a disturb characteristic of each row of memory cells, wherein the disturb characteristic of a first memory cell in the memory array is associated with an inter-cell interference between the first memory cell and at least a second memory cell in the memory array during a programming operation, and the first memory cell and the second memory cell are neighboring memory cells in the memory array;
• determine P initial program voltage pulses associated with a predetermined signal level for an operation to program an nth row of memory cells among the N rows of memory cells to the predetermined signal level, wherein n is a positive integer not larger than N;
• provide P compensated program voltage pulses by adjusting the P initial program voltage pulses according to the threshold voltage variation of the nth row of memory cells;
• and
• program the nth row of memory cells to the predetermined signal level by outputting the plurality of compensated program voltage pulses to the nth row of memory cells, wherein:
• a level of an pth initial program voltage among the P initial program voltages is equal to a sum of an initial program voltage value and p times a unit voltage increment;
• a level of an pth compensated program voltage among the P compensated program voltages is equal to a sum of the initial program voltage value, p times the unit voltage increment and a threshold voltage variation of the plurality of memory cells when programed to the predetermined signal level;
• P is an integer larger than 1;
• and
• p is a positive integer not larger than P.