Low voltage memory device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang
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Abstract
A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.
Claims20
A memory device, comprising:
- a transmission gate;
- a cross-coupled inverter circuit operably connected to the transmission gate, the cross-coupled inverter comprising a first tri-state inverter cross-coupled to an inverter;
- and
- a second tri-state inverter operably connected to the cross-coupled inverter circuit, wherein the transmission gate and the cross-coupled inverter circuit comprise a write port and the second tri-state inverter comprises a read port;
- a multiplexer having an output connected to a first bit line associated with the memory cell;
- a first latch circuit having an output connected to a first input of the multiplexer;
- a second latch circuit having an output connected to a second input of the multiplexer and an input connected to a second bit line associated with the memory cell;
- a third latch circuit having an output connected to a select input of the multiplexer;
- and
- a fourth latch circuit having an input connected to an output of the second latch circuit.
A memory device, comprising:
- a transmission gate;
- a cross-coupled inverter circuit operably connected to the transmission gate, the cross-coupled inverter circuit comprising a first tri-state inverter cross-coupled to an inverter;
- and
- a second tri-state inverter operably connected to the cross-coupled inverter circuit,
- wherein the transmission gate and the cross-coupled inverter circuit comprise a write port and the second tri-state inverter comprises a read port;
- a multiplexer having an output connected to a first bit line associated with the memory cell;
- a first latch circuit having an output connected to a first input of the multiplexer;
- and
- a masked write path including the first latch circuit, the multiplexer, and the first bit line.
A method of writing a data bit in a memory cell, the method comprising:
- reading data from a memory unit;
- storing the data in a first storage device;
- storing input data in a second storage device;
- responsive to receiving mask data indicating a write operation to the memory unit is to be a masked write operation, writing the data stored in the first storage device to the memory unit through a first latch circuit, a multiplexer, and a first bit line;
- and
- responsive to receiving second mask data indicating the write operation to the memory unit is to be an unmasked write operation, writing the data stored in the second storage device to the memory unit through a second latch circuit, the multiplexer, and the first bit line.
Dependencies are inferred from the claim text.