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US 12,119,050 B2Granted
Variable delay word line enable
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorHyunsung Hong
Life of this patent
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Abstract
A memory device includes a bit line precharge circuit configured to precharge bit lines of a memory array in response to a clock pulse. A controller is configured to output the clock pulse to the bit line precharge circuit, and to output a first word line enable signal to a word line driver. The first word line enable signal is delayed by a first delay time from the clock pulse, and a second word line enable signal is delayed by a second delay time from the clock pulse.
Claims20
A method comprising:
- receiving a clock pulse;
- receiving a first word line address corresponding to a first selected word line of a plurality of word lines;
- determining a first delay time corresponding to the first word line address, wherein determining the first delay time corresponding to the first address comprises:
- determining a first segment corresponding to the first word line address, and
- determining a delay time associated with the first segment as the first delay time, wherein a plurality of word line addresses associated with the plurality of word lines are divided into a plurality of segments based on a distance of each of the plurality of word lines from a controller, and wherein each of the plurality of segments are associated with a corresponding delay time;
- and
- generating a first word line enable signal to enable the first selected word line, wherein the first word line enable signal is delayed by the first delay time from the clock pulse.
4 more elements
A method comprising:
- receiving a first address corresponding to a first selected word line of a plurality of word lines of an array of memory cells;
- generating a first word line enable signal to enable the first selected word line of the plurality of word lines, wherein the first word line enable signal is delayed by a first delay time from a clock pulse;
- receiving a second address corresponding to a second selected word line of the plurality of word lines;
- and
- generating a second word line enable signal to enable the second selected word line of the plurality of word lines, wherein the second word line enable signal is delayed by a second delay time from the clock pulse, the second delay time being different than the first delay time.
2 more elements
A memory device, comprising:
- an array of memory cells comprising a plurality of word lines, the plurality of word lines associated with a plurality of word line addresses;
- and
- a variable delay circuit connected to the array of memory cells, wherein the variable delay circuit is configured to:
- receive a clock pulse,
- receive a first word line address corresponding to a first word line of the plurality of word lines,
- determine that the first word line address belongs to a first range of addresses associated with the plurality of word lines, wherein the plurality of word line addresses are divided into a plurality of range of addresses based on a distance of each of the plurality of word lines from the variable delay circuit, and wherein each of the plurality of range of addresses are associated with a corresponding delay time,
- determine a first delay time associated with the first range of addresses, and
- generate a first word line enable signal to enable the first word line of the plurality of word lines, wherein the first word line enable signal is delayed by the first delay time from the clock pulse.
5 more elements
Dependencies are inferred from the claim text.