Memory controller performing data training, system-on-chip including the memory controller, and operating method of the memory controller

A system-on-chip in communication with a memory device unit, the system-on-chip comprising:

• a memory control unit configured to control an operation of the memory device unit;
• and
• a double data rate physical layer (DDR PHY) configured to exchange commands and/or addresses and data with the memory device unit,
• wherein the DDR PHY comprises:
• an input/output circuit including:
• a first receiver through an N-th receiver configured to receive, in parallel, pieces of data read from the memory device unit;
• and
• a first duty adjuster through an N-th duty adjuster arranged to respectively correspond to the first through the N-th receivers and configured to respectively adjust a duty of a corresponding piece of data (where N is an integer greater than or equal to 2);
• and
• a training circuit configured to perform a training operation on the pieces of data, to obtain a target read reference voltage for each of the pieces of data and correct a duty of each of the pieces of data based on a level of the target read reference voltage for each of the pieces of data,
• wherein a read reference voltage of a same level is provided to the first through the N-th receivers, and
• wherein, in a normal read operation, the first through the N-th duty adjusters are configured to differently adjust duties of the pieces of data based on a result of the training operation.

An operating method of a memory controller that performs training on pieces of data from a memory device unit, the operating method comprising;

• obtaining, with respect to pieces of data received through a plurality of receivers, a target read reference voltage level for each of the pieces of data and a common read reference voltage level for the pieces of data by searching for a valid window margin of the pieces of data while changing a level of a read reference voltage provided in common to the plurality of receivers;
• correcting a duty of at least one of the pieces of data based on a first difference between the target read reference voltage level obtained for at least one of the pieces of data and the common read reference voltage level;
• repeating the obtaining and the correcting in a state in which the duty of the at least one of the pieces of data is corrected;
• and
• obtaining, based on a result of the repeating, a duty correction value for each of the pieces of data.