Readout circuit structure

A readout circuit structure, disposed in a gap between adjacent memory arrays, the structure comprising:

• a first sense amplification circuit and a second sense amplification circuit, disposed adjacent to each other along an extension direction of a bit line, and configured to sense a voltage of a memory cell and output a logic 1 or 0 corresponding to the voltage, wherein the first sense amplification circuit is coupled to one memory array in the adjacent memory arrays by using a first bit line, and is coupled to the other memory array in the adjacent memory arrays by using a first complementary bit line, and the second sense amplification circuit is coupled to one memory array in the adjacent memory arrays by using a second bit line, and is coupled to the other memory array in the adjacent memory arrays by using a second complementary bit line;
• a first equalization pipe, one of a source and a drain thereof being connected to the first bit line;
• a second equalization pipe, one of a source and a drain thereof being connected to the first complementary bit line, wherein
• the first equalization pipe is configured to precharge a voltage of the first bit line to a preset voltage according to an equalization signal, and the second equalization pipe is configured to precharge a voltage of the first complementary bit line to the preset voltage according to the equalization signal;
• a third equalization pipe, one of a source and a drain thereof being connected to the second bit line;
• and
• a fourth equalization pipe, one of a source and a drain thereof being connected to the second complementary bit line, wherein
• the third equalization pipe is configured to precharge a voltage of the second bit line to the preset voltage according to the equalization signal, and the fourth equalization pipe is configured to precharge a voltage of the second complementary bit line to the preset voltage according to the equalization signal, and
• the first equalization pipe and the third equalization pipe are disposed on a side of the first sense amplification circuit away from the second sense amplification circuit, and the second equalization pipe and the fourth equalization pipe are disposed on a side of the second sense amplification circuit away from the first sense amplification circuit;
• wherein the equalization signal comprises a first equalization signal and a second equalization signal;
• the first equalization pipe and the third equalization pipe share a same gate, configured to receive the first equalization signal;
• and the second equalization pipe and the fourth equalization pipe share a same gate, configured to receive the second equalization signal.

A readout circuit structure, disposed in a gap between adjacent memory arrays, the structure comprising:

• a first sense amplification circuit and a second sense amplification circuit, disposed adjacent to each other along an extension direction of a bit line, and configured to sense a voltage of a memory cell and output a logic 1 or 0 corresponding to the voltage, wherein the first sense amplification circuit is coupled to one memory array in the adjacent memory arrays by using a first bit line, and is coupled to the other memory array in the adjacent memory arrays by using a first complementary bit line, and the second sense amplification circuit is coupled to one memory array in the adjacent memory arrays by using a second bit line, and is coupled to the other memory array in the adjacent memory arrays by using a second complementary bit line;
• a first equalization pipe, one of a source and a drain thereof being connected to the first bit line;
• a second equalization pipe, one of a source and a drain thereof being connected to the first complementary bit line, wherein
• the first equalization pipe is configured to precharge a voltage of the first bit line to a preset voltage according to an equalization signal, and the second equalization pipe is configured to precharge a voltage of the first complementary bit line to the preset voltage according to the equalization signal;
• a third equalization pipe, one of a source and a drain thereof being connected to the second bit line;
• and
• a fourth equalization pipe, one of a source and a drain thereof being connected to the second complementary bit line, wherein
• the third equalization pipe is configured to precharge a voltage of the second bit line to the preset voltage according to the equalization signal, and the fourth equalization pipe is configured to precharge a voltage of the second complementary bit line to the preset voltage according to the equalization signal, and
• the first equalization pipe and the third equalization pipe are disposed on a side of the first sense amplification circuit away from the second sense amplification circuit, and the second equalization pipe and the fourth equalization pipe are disposed on a side of the second sense amplification circuit away from the first sense amplification circuit;
• wherein the first sense amplification circuit comprises:
• a sense amplification module, connected to the first bit line by using a readout bit line, connected to the first complementary bit line by using a complementary readout bit line, and configured to sense the voltage of the memory cell and output the logic 1 or 0 corresponding to the voltage;
• an isolation module, connected between the complementary readout bit line and the first complementary bit line, connected between the readout bit line and the first bit line, and configured to isolate signal interaction between the first bit line and the readout bit line according to an isolation signal and isolate signal interaction between the first complementary bit line and the complementary readout bit line according to the isolation signal;
• and
• an offset cancellation module, connected between the readout bit line and the first complementary bit line, connected between the complementary readout bit line and the first bit line, and configured to adjust a source-drain conduction difference between N-Metal-Oxide-Semiconductor (NMOS) pipes or P-Metal-Oxide-Semiconductor (PMOS) pipes in the sense amplification module according to an offset cancellation signal.