Memory array layers with alternating sense amplifier layers

A memory, comprising:

• bit lines extending along a first direction and word lines extending along a second direction;
• a plurality of memory modules arranged along the first direction, wherein each of the plurality of memory modules comprises a memory array and an amplifier array that are arranged along the first direction, the memory array comprises at least one memory cell, the amplifier array comprises at least one amplification unit, each of the bit lines is electrically connected to one terminal of a corresponding amplification unit, and each of the word lines is electrically connected to a corresponding memory cell, wherein the plurality of memory modules are divided into at least two module regions arranged along the first direction, and each of the at least two module regions comprises at least two of the plurality of memory modules;
• a column selection circuit and a read-write control driver circuit, wherein the column selection circuit and the read-write control driver circuit are located on a same side of the plurality of memory modules perpendicular to the first direction;
• column-select lines extending along the first direction and column connection lines extending along a third direction, wherein each of the column-select lines is electrically connected to the amplification unit arranged along the first direction and is electrically connected to the column selection circuit through the column connection line, and the column selection circuit is configured to drive the amplification unit electrically connected to the column-select line;
• and
• a global data line extending along the first direction and a global connection line extending along the third direction, wherein the global data line is electrically connected to the read-write control driver circuit through the global connection line, and the read-write control driver circuit is configured to drive a memory module corresponding to the global data line to write data into the memory cell through the global data line, or to read data from the memory cell and transmit the data to the global data line;
• wherein the column selection circuit comprises at least two column selection modules arranged along the first direction, each of the at least two column selection modules is located on one side of a corresponding module region, and is electrically connected to a corresponding column-select line through the column connection line, and the read-write control driver circuit comprises at least two read-write control driving modules arranged along the first direction, wherein each of the at least two read-write control driving modules is located on one side of a corresponding module region, and is electrically connected to a corresponding global data line through the global connection line;
• and
• wherein for a same module region, a quantity of column connection lines is the same as a quantity of column-select lines, and each of the column connection lines is electrically connected to one of the column-select lines;
• or for a same module region, a same column connection line is electrically connected to at least two of the column-select lines.

A memory, comprising:

• bit lines extending along a first direction and word lines extending along a second direction;
• a plurality of memory modules arranged along the first direction, wherein each of the plurality of memory modules comprises a memory array and an amplifier array that are arranged along the first direction, the memory array comprises at least one memory cell, the amplifier array comprises at least one amplification unit, each of the bit lines is electrically connected to one terminal of a corresponding amplification unit, and each of the word lines is electrically connected to a corresponding memory cell, wherein the plurality of memory modules are divided into at least two module regions arranged along the first direction, and each of the at least two module regions comprises at least two of the plurality of memory modules;
• a column selection circuit and a read-write control driver circuit, wherein the column selection circuit and the read-write control driver circuit are located on a same side of the plurality of memory modules perpendicular to the first direction;
• column-select lines extending along the first direction and column connection lines extending along a third direction, wherein each of the column-select lines is electrically connected to the amplification unit arranged along the first direction and is electrically connected to the column selection circuit through the column connection line, and the column selection circuit is configured to drive the amplification unit electrically connected to the column-select line;
• and
• a global data line extending along the first direction and a global connection line extending along the third direction, wherein the global data line is electrically connected to the read-write control driver circuit through the global connection line, and the read-write control driver circuit is configured to drive a memory module corresponding to the global data line to write data into the memory cell through the global data line, or to read data from the memory cell and transmit the data to the global data line;
• wherein the column selection circuit comprises at least two column selection modules arranged along the first direction, each of the at least two column selection modules is located on one side of a corresponding module region, and is electrically connected to a corresponding column-select line through the column connection line, and the read-write control driver circuit comprises at least two read-write control driving modules arranged along the first direction, wherein each of the at least two read-write control driving modules is located on one side of a corresponding module region, and is electrically connected to a corresponding global data line through the global connection line;
• and
• wherein the column selection module comprises at least two column selection units arranged along the first direction, and each of the at least two column selection units is electrically connected to at least two of the column-select lines through the column connection lines.