US 12,119,044 B2 · Memory devices and methods for controlling row hammer

Abstract

Memory devices and methods for controlling a row hammer are provided. The memory device includes a memory cell array including a word line and a plurality of counter memory cells storing an access count value of the word line, and a control logic circuit configured to monitor a row address accessing the word line during a row hammer monitoring time frame and to determine the row address to be a row hammer address when the number of times the word line is accessed is greater than or equal to a threshold value, wherein the row hammer address is to be stored in an address storage. The control logic circuit is further configured to hold up a determination operation for a next row hammer address, based on activation of a latch full signal indicating that there is no free space to store the row hammer address in the address storage.

Claims20

Dependent claims

A memory device comprising:

a memory cell array comprising a word line and a plurality of counter memory cells configured to store an access count value of the word line;
and
a control logic circuit configured to monitor a row address accessing the word line during a row hammer monitoring time frame and to determine the row address to be a row hammer address when a number of times the word line is accessed is greater than or equal to a threshold value, wherein the row hammer address is to be stored in an address storage,
wherein the control logic circuit is configured to hold up a determination operation for a next row hammer address, based on activation of a latch full signal indicating no free space to store the row hammer address in the address storage.

1 more element

A control logic circuit comprising:

a counter configured to:
count a number of times a word line is accessed by a row address during a row hammer monitoring time frame;
read an access count value of the word line from a plurality of counter memory cells connected to the word line accessed by the row address;
increment the read access count value;
and
output an output value of the counter as the number of times the word line is accessed by the row address;
a comparator configured to compare the output value of the counter with a threshold value to determine whether the row address is a row hammer address;
and
a latch circuit configured to store the row hammer address in an address storage based on a determination of the comparator, and configured to activate a latch full signal indicating no free space to store the row hammer address in the address storage,
wherein the output value of the counter related to a number of times accessing by a next row address is not provided to the comparator, in response to the activated latch full signal.

7 more elements

Dependencies are inferred from the claim text.

Memory devices and methods for controlling row hammer

Life of this patent

Memory devices and methods for controlling row hammer

Life of this patent

Abstract

Claims20