Memory power control by enable circuit

A circuit, comprising:

• a first voltage domain input terminal;
• a second voltage domain input terminal;
• a first transistor having a first source/drain terminal connected to the first voltage domain input terminal and a second source/drain terminal connected to a voltage output terminal;
• a second transistor having a first source/drain terminal connected to the second voltage domain input terminal and a second source/drain terminal connected to the voltage output terminal;
• a control circuit having an enable input terminal and an output terminal connected to gate terminals of the first and second transistors;
• and
• an enable circuit including an inverter having an input terminal connected to the first voltage domain input terminal, and an output connected to the enable input terminal.

A method, comprising:

• receiving a first voltage signal in a first power domain by a first terminal of a first switch;
• receiving a second voltage signal in a second power domain by a first terminal of a second switch, wherein a second terminal of the second switch is coupled to a second terminal of the first switch;
• receiving the first voltage signal in the first voltage domain by an input terminal of an enable circuit;
• receiving an enable signal based on the voltage level of the first voltage signal from the enable circuit at an enable input terminal;
• receiving a shutdown signal having a first logic level that indicates a shutdown mode;
• turning off the first switch and the second switch in response to the first logic level of the shutdown signal;
• and thereafter
• turning on the first switch in response to a decrease of the first voltage signal indicated by the enable signal while in the shutdown mode.