Refresh control circuit and method, and memory

A refresh control method, applied to a refresh control circuit and connected with a memory array, and comprising:

• determining a to-be-refreshed address signal, the to-be-refreshed address signal comprising a block address signal and a row address signal;
• decoding the block address signal to obtain a first block selection signal in response to that the memory array is subjected to no row hammer attack;
• and decoding the block address signal to obtain a second block selection signal in response to that the memory array is subjected to a row hammer attack;
• wherein the first block selection signal is used for selecting multiple data blocks from the memory array, and the second block selection signal is used for selecting one data block from the memory array;
• decoding the row address signal to obtain a row selection signal, wherein the row selection signal is used for selecting a target refresh word line (WL) from the one data block selected by the second block selection signal, or selecting target refresh WLs from the multiple data blocks selected by the first block selection signal;
• and
• refreshing the target refresh WL(s).

A memory, comprising a refresh control circuit and a memory array, the refresh control circuit being connected with the memory array and comprising:

• an address output circuit, configured to output a to-be-refreshed address signal, the to-be-refreshed address signal comprising a block address signal and a row address signal;
• a block decoding circuit, configured to:
• receive the block address signal;
• and decode the block address signal and output a first block selection signal, in response to that the memory array is subjected to no row hammer attack, or decode the block address signal and output a second block selection signal, in response to that the memory array is subjected to a row hammer attack;
• wherein the first block selection signal is used for selecting multiple data blocks from the memory array, and the second block selection signal is used for selecting one data block from the memory array;
• and
• a row decoding circuit, configured to receive the row address signal, decode the row address signal, and output a row selection signal, wherein the row selection signal is used for selecting a target refresh word line (WL) from the one data block selected by the second block selection signal, or selecting target refresh WLs from the multiple data blocks selected by the first block selection signal.