Refresh circuit, memory, and refresh method

A refresh circuit, comprising:

• a refresh counter comprising a plurality of address pins and configured to output address signals through the plurality of address pins;
• an address mixer comprising a plurality of row address pins and a plurality of bank address pins which are connected to the different address pins respectively, wherein the address mixer is configured to output row address selection signals according to the address signals received by the row address pins, output first bank address signals according to the address signals received by the bank address pins, receive a refresh signal and a power supply voltage signal, and output fixed second bank address signals according to the refresh signal and the power supply voltage signal;
• and
• an address pre-decoding circuit configured to receive the first bank address signals and the second bank address signals, and configured to output a preset number of bank address selection signals according to the first bank address signals and the second bank address signals.