Spacer film scheme for polarization improvement

An integrated chip, comprising:

• one or more lower interconnects arranged within a dielectric structure over a substrate;
• a lower electrode disposed over the one or more lower interconnects;
• a ferroelectric data storage structure disposed on the lower electrode;
• an upper electrode disposed on the ferroelectric data storage structure;
• one or more stressed sidewall spacers arranged on opposing sides of the upper electrode, wherein the one or more stressed sidewall spacers comprise a tensile stress;
• and
• wherein the ferroelectric data storage structure has a central region directly below the upper electrode and one or more peripheral regions directly below the one or more stressed sidewall spacers, the one or more peripheral regions having a first polar orthorhombic phase concentration that is higher than a second polar orthorhombic phase concentration within the central region.

A method of forming an integrated chip (IC), comprising:

• forming one or more lower interconnects within a lower dielectric structure formed over a substrate;
• forming a lower electrode layer over the one or more lower interconnects;
• forming a ferroelectric data storage layer over the lower electrode layer;
• forming an upper electrode over the ferroelectric data storage layer;
• forming one or more stressed sidewall spacers along opposing sides of the upper electrode;
• and
• performing an anneal process after forming the one or more stressed sidewall spacers to increase an orthorhombic phase concentration within parts of the ferroelectric data storage layer.