Display controller and method having automatic data underrun recovery function

A display controller with data under run self-recovery function, characterized in that, it comprises:

• an image processor and a timing controller (TCON),
• the image processor further comprises a direct memory access (DMA) controller, an image data processor, an image layer combiner, and a first-in-first-out (FIFO) memory;
• the timing controller further comprises a display timing circuit (DTC), an under run state machine, and an under run data counter;
• wherein the DMA controller is directly coupled to the image data processor, the image data processor is directly coupled to the image layer combiner, the image layer combiner is directly coupled to the FIFO memory, the DTC is directly coupled to the FIFO memory, the DTC is directly coupled to an external display device, and the under run state machine is directly coupled to each of the DTC, the under run data counter, the direct memory access DMA controller, the image data processor, the image layer combiner and the FIFO memory respectively,
• wherein the display timing circuit DTC is configured to execute the following steps:
• access the FIFO memory to acquire the image data stored in the FIFO memory;
• according to the timing requirements of the external display device, generate four types of control signals required by th display device, including a frame synchronization signal (VSYNC), a line synchronization signal (HSYNC), a data enable signal (DE) and a display clock signal (PCLK);
• when the DE is valid, continuously acquire the image display data from the FIFO memory, and send display data (PDATA) to the display device for display at the rising edge of each PCLK, wherein the under run state machine is configured to execute the following steps:
• receive the VSYNC and the HSYNC sent by the DTC and a null value signal (FIFO_EMPTY) returned by the FIFO memory,
• while the DE is valid, determine if the FIFO_EMPTY returned by the FIFO memory is valid;
• a valid FIFO_EMPTY being indicative that the timing controller TCON bas encountered a data under run problem when reading the FIFO memory;
• then the under run state machine jumping first under run state, and
• wherein when the under run state machine is in the first under run state, the under run state machine is configured to execute the following steps:
• send a count increment instruction to the under run data counter if the FIFO_EMPTY is valid and a FIFO read request signal is valid;
• according to a value of under run data logged by the under run data counter when the DE is invalid in a line blanking or a frame blanking region, send a FIFO read request instruction to the FIFO memory to read data, the number of which is equal to the value of under run data;
• send a count decrement instruction from the under run statement to the under run data counter whenever a data item is read,
• the under run state machine exits the first under run state and moves to a normal state when the under run data counter is zero.