Gate drive circuit, display panel, and display apparatus

A display panel, comprising:

• a gate drive circuit, comprising:
• a quantity n of shift register units arranged along a first direction, wherein:
• a shift register unit includes an input circuit, a first node control circuit, a second node control circuit and an output control circuit, wherein each of the input circuit, the first node control circuit and the second node control circuit is electrically connected to a third node;
• the first node control circuit is configured to control a stage of a first node;
• the second node control circuit is configured to control a stage of a second node;
• the output control circuit is electrically connected to each of a scan signal output terminal, the first node and the second node, and configured to control the scan signal output terminal to output a scan signal according to the stage of the first node and the stage of the second node;
• along the first direction, control terminals of an input circuit of an m-th shift register unit are electrically connected to a scan signal output terminal of an (m+1)-th shift register unit and a scan signal output terminal of an (m−1)-th shift register unit respectively, wherein m∈n;
• and
• the display panel further includes a plurality of forward and reverse direction scan selection circuits and a plurality of pixel rows, wherein:
• a pixel row of the plurality of pixel rows includes a plurality of sub-pixels, and a sub-pixel of the plurality of sub-pixels includes a pixel circuit and a light-emitting element;
• one forward and reverse direction scan selection circuit is electrically connected to at least one pixel circuit;
• a forward and reverse direction scan selection circuit of the plurality of forward and reverse direction scan selection circuits includes a forward and reverse direction scan selection output terminal and a forward and reverse direction scan selection input terminal;
• the forward and reverse direction scan selection output terminal of the forward and reverse direction scan selection circuit is electrically connected to the pixel circuit;
• and
• along the first direction, both the scan signal output terminal of the (m+1)-th shift register unit and the scan signal output terminal of the (m−1)-th shift register unit are electrically connected to the forward and reverse direction scan selection input terminal of the forward and reverse direction scan selection circuit.

A display apparatus, comprising:

• a display panel, comprising:
• a gate drive circuit, comprising:
• a quantity n of shift register units arranged along a first direction, wherein:
• a shift register unit includes an input circuit, a first node control circuit, a second node control circuit and an output control circuit, wherein each of the input circuit, the first node control circuit and the second node control circuit is electrically connected to a third node;
• the first node control circuit is configured to control a stage of a first node;
• the second node control circuit is configured to control a stage of a second node;
• the output control circuit is electrically connected to each of a scan signal output terminal, the first node and the second node, and configured to control the scan signal output terminal to output a scan signal according to the stage of the first node and the stage of the second node;
• and
• along the first direction, control terminals of an input circuit of an m-th shift register unit are electrically connected to a scan signal output terminal of an (m+1)-th shift register unit and a scan signal output terminal of an (m−1)-th shift register unit respectively, wherein m∈n;
• the input circuit includes a first input selection unit and a second input selection unit;
• the first input selection unit includes a first input terminal, a first output terminal and a first control terminal;
• and the second input selection unit includes a second input terminal, a second output terminal and a second control terminal;
• the first input terminal is electrically connected to a first signal line, and the first output terminal is electrically connected to the third node;
• the second input terminal is electrically connected to a second signal line, and the second output terminal is electrically connected to the third node;
• and
• along the first direction, a first control terminal of the m-th shift register unit is electrically connected to the scan signal output terminal of the (m+1)-th shift register unit;
• and a second control terminal of the m-th shift register unit is electrically connected to the scan signal output terminal of the (m−1)-th shift register unit;
• and
• when the gate drive circuit operates in a forward direction scan mode, the first signal line transmits a high-level signal, and the second signal line transmits a low-level signal.