Display panel and display device

A display panel comprising:

• a pixel circuit including a driving module, a data writing module, a bias adjustment module, and a compensation module, the driving module including a driving transistor, the data writing module being configured to provide a data signal for the driving transistor, the bias adjustment module being configured to provide a bias adjustment signal for the driving transistor, and the compensation module being connected between a gate and a drain of the driving transistor;
• and
• a light-emitting element;
• wherein:
• a time period of one frame of the display panel includes a non-light-emitting stage and a light-emitting stage, the non-light-emitting stage including a bias adjustment stage, the compensation module being turned off and at least one of a source or the drain of the driving transistor being configured to receive the bias adjustment signal in the bias adjustment stage;
• an operating state of the pixel circuit includes a first mode and a second mode, a time length of the non-light-emitting stage in the first mode is L1, and a time length of the non-light-emitting stage in the second mode is L2;
• L1>L2;
• a working process of the display panel in the first mode includes a first frame, and a working process of the display panel in the second mode includes a second frame;
• a time length of the bias adjustment stage in the first frame is W1, and a time length of the bias adjustment stage in the second frame is W2;
• W2/W1≥1, and/or W2/W1<L1/L2.

A display panel comprising:

• a pixel circuit including a driving module, the driving module including a driving transistor;
• and
• a light-emitting element;
• wherein:
• a time period of one frame of the display panel includes a non-light-emitting stage and a light-emitting stage, the non-light-emitting stage including a bias adjustment stage, at least one of a source or a drain of the driving transistor being configured to receive a bias adjustment signal in the bias adjustment stage;
• an operating state of the pixel circuit includes a first mode and a second mode, a time length of the non-light-emitting stage in the first mode is L1, and a time length of the non-light-emitting stage in the second mode is L2;
• L1>L2;
• a working process of the display panel in the first mode includes a first frame, and a working process of the display panel in the second mode includes a second frame;
• a time length of the bias adjustment stage in the first frame is W1, and a time length of the bias adjustment stage in the second frame is W2;
• W2/W1≥1, and/or W2/W1<L1/L2.