Gate drive circuit and display panel
AssigneeWuhan China Star Optoelectronics Technology Co., Ltd.
InventorHaiming Cao
Life of this patent
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Abstract
The present application discloses a gate drive circuit and a display panel. The gate drive circuit includes a plurality of cascaded gate drive units, in which by adopting a same complex clock signal for a pull-down control module, a maintaining module and a pull-down module, a N-th-stage gate drive unit can rapidly pull down a falling edge of a N-th-stage scan signal to the potential of a constant low voltage level signal and effectively reduces the time required to pull down the N-th-stage scan signal from high voltage level to low voltage level.
Claims19
A gate drive circuit, comprising a plurality of cascaded gate drive units, in which a N-th-stage gate drive unit comprises:
- a pull-down control module, a control end of the pull-down control module configured to receive a complex clock signal, an output end of the pull-down control module electrically connected to a N-th-stage node, the complex clock signal comprising a first clock signal;
- a pull-up module, the control end of the pull-up module electrically connected to the N-th-stage node, the output end of the pull-up module configured to output a N-th-stage scan signal;
- a pull-down module, an input end of the pull-down module configured to receive a constant low voltage level signal, the output end of the pull-down module electrically connected to the output end of the pull-up module, the control end of the pull-down module configured to receive the first clock signal;
- and
- a maintaining module, one of the input end and the output end of the maintaining module electrically connected to the N-th-stage node, the other one of the input end and the output end of the maintaining module electrically connected to the output end of the pull-up module, the control end of the maintaining module configured to receive the complex clock signal,
- wherein the N-th-stage gate drive unit further comprises:
- a pull-up control module, the input end of the pull-up control module level electrically connected to the input end of the pull-down control module, the control end of the pull-up control module electrically connected to a (N−4)-th-stage node, the output end of the pull-up control module electrically connected to the N-th-stage node.
A gate drive circuit, comprising a plurality of cascaded gate drive units, in which a N-th-stage gate drive unit comprises:
- a first thin-film transistor, a gate of the first thin-film transistor configured to receive a first clock signal, one of a source and a drain of the first thin-film transistor electrically connected to a N-th-stage node;
- a second thin-film transistor, one of the source and the drain of the second thin-film transistor electrically connected to the other one of the source and the drain electrode of the first thin-film transistor, the gate of the second thin-film transistors configured to receive a second clock signal;
- a third thin-film transistor, the gate of the third thin-film transistor electrically connected to the N-th-stage node, one of the source and the drain of the third thin-film transistor configured to output a N-th-stage scan signal;
- a fourth thin-film transistor, one of the source and the drain of the fourth thin-film transistor electrically connected to one of the source and the drain of the third thin-film transistor, the gate of the fourth thin-film transistor configured to receive the first clock signal;
- a fifth thin-film transistor, one of the source and the drain of the fifth thin-film transistor electrically connected to the other one of the source and the drain of the fourth thin-film transistor, the gate of the fifth thin-film transistor configured to receive the second clock signal, the other one of the source and the drain of the fifth thin-film transistor electrically connected to the N-th-stage node;
- and
- a sixth thin-film transistor, one of the source and the drain of the sixth thin-film transistor configured to receive a constant low voltage level signal, the gate of the sixth thin-film transistor configured to receive the first clock signal, the other one of the source and the drain of the sixth thin-film transistor electrically connected to one of the source and the drain of the third thin-film transistor.
Dependencies are inferred from the claim text.