Device and method for detecting defects on wafer
AssigneesSamsung Electronics Co., Ltd., Seoul National University R&Db Foundation
InventorsMin-Cheol Kang, Do-Nyun Kim, Jaehoon Kim, Woojoo Sim
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AssigneesSamsung Electronics Co., Ltd., Seoul National University R&Db Foundation
InventorsMin-Cheol Kang, Do-Nyun Kim, Jaehoon Kim, Woojoo Sim
Estimating the term…
Disclosed is a wafer defect inference system, which includes a test equipment that receives a first image obtained by imaging circuit patterns formed on a semiconductor wafer by using a scanning electron microscope and a second image obtained by imaging a layout image of a mask for implementing the circuit pattern on the semiconductor wafer and combines the first image and the second image to generate a combination image, and at least one computing device that is capable of communicating with the test equipment and infers a defect associated with the circuit pattern formed on the semiconductor wafer. The computing device receives the combination image, performs machine learning for inferring the defect based on the combination image, and generates an output image including information about the defect based on the machine learning.
A wafer defect inference system comprising:
A method of inferring a defect in a circuit pattern formed on a semiconductor wafer, the method comprising:
A non-transitory computer-readable medium storing a program code including an image generation model executable by a processor, the program code, when executed, causing the processor to:
Dependencies are inferred from the claim text.